Unit -II
CPU Organization
By- Mr. S. S. Hire
CPU organization
Additional Features
 Most recent CPUs contain following extensions which improves
their performance and ease of programming.
1. Multipurpose register set for storing data and addresses.
AC, DR, AR are replaced by register file which is multipurpose.
2. Additional data, instruction and address types.
supports several different word sizes and formats. Call and
return instructions are added which simplifies program design.
Additional Features
3. Status Register- Register to indicate computation status.
- Indicates infrequent or exceptional conditions.
- Also indicates the user and supervisor states.
- Conditional branch instructions test the status register.
4. Program control stack.
- SP keeps track of the stack’s entry point.
- A part external memory is used as push-down stack
memory.
Pipelining
• Speed up Techniques, instruction level parallelism
• Parallelism may be present in DPU, overlapping
carried out by DPU or PCU
Coprocessor
• Coprocessor is a companion of processor which executes a
floating point instruction.
• The instruction and data transfer between earlier Processor
and coprocessor takes place through an I/O handshaking
mode which takes (15Cycles)
• That’s why an on-chip coprocessor was included while
designing the 80486 CPU. (4 Cycles required)
• Another limitation of this coprocessor architecture is that the
total internal registers is less. i.e. only eight.
• And these processors are essentially stack oriented rather
than register oriented which restrict their speed.
Coprocessor
• When coprocessor is not connected in the system, then a
software routine is executed. The interrupt used during this
process is called coprocessor trap.
• The coprocessor status is stored in the status register, which
can be read by the host CPU to check the proper execution.
Coprocessor
RISC Processors
• IBM RISC Processors starting with R6000 series , now led to
the development of IBM Power PCs.
• ARM processors developed by ACORN company.
• The MIPs series from Stanford MIPS used in Sun
Microsystem's SPARC microprocessors.
• Now led to the part of Silicon Graphics, DEC’s Alpha microchip
Advantages of RISC
•
•
•
•
•
RISC instructions are simple and can be hard-wired.
Reduced complexity of control unit.
Shorter design cycle.(Design-Develop-Test)
Compilers produce more efficient codes.
The loading and decoding of instructions in a RISC processor is
simple and fast.
• Disadvantages of RISC: 1. Code Quality.
2. Code Size.
Features of RISC
•
•
•
•
•
•
•
Simple instruction set
Same length instruction.
Large number of registers.
Very few addressing modes and formats.
Pipelining.
Load and store architecture.
Micro coding not required.
ARM6 Microprocessor
•
•
•
•
ARM6 is a 32 bit processor.
It has load and store architecture.
Employs an instruction pipeline.
Uses memory mapped I/O.
What is CISC?
• CISC is an acronym for Complex Instruction Set
Computer and are chips that are easy to program and
which make efficient use of memory. Since the earliest
machines were programmed in assembly language and
memory was slow and expensive, the CISC philosophy
made sense, and was commonly implemented in such
large computers as the PDP-11 and the DECsystem 10
and 20 machines.
• Most common microprocessor designs such as the Intel
80x86 and Motorola 68K series followed the CISC
philosophy.
• But recent changes in software and hardware technology
have forced a re-examination of CISC and many modern
CISC processors are hybrids, implementing many RISC
principles.
CISC Attributes
• The design constraints that led to the development of
CISC (small amounts of slow memory and fact that
most early machines were programmed in assembly
language) give CISC instructions sets some common
characteristics:
• Variable length instructions.
• Instructions which require multiple clock cycles to
execute.
• E.g. Pentium is considered a modern CISC processor
CISC Processor: 68020
• The 68020 is a 32 bit, one chip microprocessor introduced in
1985.
• Uses Memory mapped I/O.
• It contains Sixteen 32 bit registers (D0:D7) and (A0:A7).
• ALU can execute a large set of fixed-point instructions.
• Instruction interpretation and other control functions of CPU
are implemented by a micro programmed control unit.
• It has 70 distinct instruction types and various addressing
modes.
• It does not have load/store architecture.
Addressing modes
• The different ways in which the location of an operand is
specified in an instruction are referred to as addressing modes.
• An address computed by the processor when executing a
memory access or branch instruction is known as Effective
address (EA).
• An effective address can be made up from 3 elements:
1. Base
2. Index
3. Displacement.
Instruction Set: Addressing modes
1. Register addressing mode.
2. Absolute or direct addressing mode.
3. Immediate addressing mode.
4. Indirect addressing mode.
5. Register indirect addressing mode.
6. Displacement addressing mode.
7. Relative addressing mode.
8. Base register addressing.
9. Index addressing mode.
10. Auto-increment addressing mode.
11. Auto-decrement addressing mode.
12. Stack addressing mode.
• Register addressing mode: The operand is the contents of a processor register.
The name of the register is given in the instruction.
A variable is represented by allocating a register or a memory
location to hold its value.
E.g. MOV R1,R2
• Absolute or direct addressing mode: The operand is in a memory location, the address of the
location is given explicitly in the instruction.
The absolute mode can represent global variables
E.g. MOV R2, LOC
MOV A,2000
• Immediate addressing mode: The operand is given explicitly in the instruction.
# sign is used to indicate that this value is to be used as an
immediate operand.
It is used to increment a counter, test for some bit pattern.
E.g. MOV A,#200
• Indirect addressing mode: The EA of the operand is the contents of a register or memory
location whose address appears in the instruction.
The instruction contains the address of memory which refers
the address of the operand.
E.g. MOV R1, [1000]
• Register indirect addressing mode.
Indirection is denoted by placing the name of the register or
the memory location address in parenthesis.
E.g. MOV R0,(R1)
The register or memory location that contains the address of
an operand is called a pointer.
It can be used to access successive numbers in the list.
Global variables can be accessed using register indirect.
Limitations –
Limited usefulness. Seldom found in modern computers.
Not suited to modern computers.
• Displacement addressing mode: It combines the capabilities of direct addressing and register
indirect addressing.
Instruction has two address fields:
value and Referenced register.
EA = Value + (R)
Three common variation of displacement addressing are:
- Relative addressing.
- Base register addressing.
- Index addressing mode
• Relative addressing mode: EA = PC + Address part of instruction
The referenced register is program counter (PC) instead of Ri
The addressed location is identified “relative” to the PC.
E.g. JNZ BACK
Its most common use is to specify the target address in branch
instructions.
• Base register addressing.
EA = (R) + Displacement.
E.g. MOV A,[R+8]
Displacement is usually unsigned integer number.
• Index addressing mode: EA= Memory address + (R)
= X + [Ri]
= X(Ri)
= X(Ri, Rj)
The contents of the index register are not changed.
X may be explicit number or a symbolic name.
It is useful in dealing with lists and arrays.
This is mainly used to access multiple components inside
each item in a record.
This mode implements a three-dimensional array.
• Additional modesi.
Autoincrement mode
Increments register contents by operand size.
E.g. (Ri)+
i.
Autodecrement mode
Decrement register contents by operand size.
E.g. - (Ri)
These modes are useful for accessing data items in
successive locations in the memory.
By using these modes, an important data structure called
stack can be implemented.
It reduces the number of instructions needed to perform
the desired task.
• Stack addressing mode: Stack is associated with a pointer called stack pointer(SP)
It is the special case of register indirect addressing .
E. g. PUSH R