Design for Testability (DfT)
OUTLINE
•
•
•
•
Motivation
Background and Definitions
Boolean Difference and Testing of Digital Circuits
Combinational Circuit Testing
– Path Sensitization
– D-Algorithm
How do we know that our Design
works?
x=(x0,x1,..,xn)
Fault!!!
f(x)
q=(q0,q1,…qn)
System Validation Techniques
Simulation
– Validate a model of the system.
Emulation
– Build a prototype and validate.
Testing
– Check the correctness of actual system.
Formal Verification
– Mathematically show the ’Equivalence’ of the
specification and the implementation.
Definitions: Errors and Faults
• Error : Incorrect operation of the system.
• Cause of Error are Faults
– Design error, fabrication error, fabrication defect, physical defects.
• Logical Fault: Faults which result in a change in logic
value at a point in a circuit.
• Fault Model: The effect of a fault is represented by a
model
–
–
–
–
Stuck-at-fault
Bridging fault
Stuck-open fault
Linking faults: Memories
Fault Probabilities
Dynamic Faults
49%
Static Faults
Intermittent Faults
1%
50%
Fault Probabilities
• Dynamic Faults
• Timing Failures
• Components out of specification
• Static Faults
• Short-circuits
• Breaks
• Intermittent Faults (Environmental Faults)
– Single-Event Upsets - SEUs
• ESD
• Particles
• Magnetic Fields
Testing Techniques
• General Method
– The behavior (Response) of the system is observed by applying a
sequence of test inputs (Stimuli).
• Generation of Stimuli
– Test various cases
– Random Patterns: Random Testing
– Algorithmic Test Pattern Generation
• Combinational Circuit
• Sequential Circuit
• Test Time
– Time to generate tests and apply them to the circuit under test
• Fault Coverage
– Percentage of all the faults detected by a set of test patterns
Test Cost and Quality
Cost of quality
Cost
Cost of
the fault
Cost of
testing
Quality
0%
Optimum
test
100%
Design for Testability( DFT)
• To take into account the testing aspects during
the design process so that testing is simpler and
faster.
–
–
–
–
Reduce test effort
Reduce test time
Reduce cost of test equipment
Increase product quality
• Limitations
– Hardware overhead ( 5-30%)
– Performance degradation
– Increase in design complexity
Fault Models
• Stuck Fault Model
– Stuck-at-0 (S-a-0) & Stuck-at-1 model (S-a-1)
• Single-Stuck Fault Model
– Heuristic Model, multiple faults do occur. Model appears to be
valid most of the times
• Other Stuck Fault Models
– Variants including Stuck-at-open, Stuck-at-short
Faults Model : Assumptions
• For Combinational Circuits
– Logical faults only
– Only those faults which can be modeled as a signal
stuck-at-0 or stuck-at-1.
– Single fault
– Permanent fault
• For Sequential Circuits
– State table of the faulty sequential circuit is different
from the good circuit.
Fault-oriented Test Pattern
Generation
• Combinational circuit with n inputs
– 2n possible patterns (exhaustive test)
– Find minimum number of necessary input patterns
• Problem: Some nodes may not be testable because of
circuit structure
Fault Detection in Logic Circuits
• Number of possible faults
x1
x2
x3
Gate
N input gate may have 2(N+1)
stuck at faults
• Equivalent faults
z
x1 s-a-1
x1 s-a-0
x2 s-a-1
x2 s-a-0
x3 s-a-1
x3 s-a-0
z s-a-1
z s-a-0
For an n-input AND gate, any input s-a-0 is equivalent
to the output s-a-0. The same test (all 1’s) is required
to test any of these faults.
Testability
• Controllability
– Can we control all nodes to establish whether there is a fault?
• Observability
– Can we observe and distinguish between the behavior of a faulty
node and a free node?
Detectable Stuck-At Fault
a
&
b
e
1
S-a-0
c
1
d
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
Good
Circuit
Faulty
Circuit
Fault Masking and Redundant Circuit
The fault cannot be detected because the circuit
has redundancy.
Good Circuit
1
1
0
1
Example:
0
0
S-a-0
X
0
X
1
0
X
0
1
0
X
1
a
&
b
1
1
e
1
1
d
Faulty Circuit
0
Undetectable faults
• In general, untestable faults are due to redundancy
• Conversely, redundant circuits are not fully testable
• Fan-out may also cause untestable faults
Undetectable faults
D
A
C
B
E
Z
F
Consider Z=AC+BC - to avoid hazard we add the term AB
=>
Z=AC+BC+AB
=> Impossible to test F/0
Undetectable faults’ fix
D
A
C
B
E
Z
F
Z2
Solution:
Add internal wires to propagate an internal value to a new output
Ad Hoc DFT Techniques
OP
• Test Point Insertion
C1
C1
C2
C2
CP0 CP1
Demultiplexing Control Points
D
e
m
u
x
C
1
2
m
Multiplexing Observation points
CP1
CP2
OP1
OP2
CPN
OPN
M
u
x
1 2
O
m
Test Generation for Combinational
Circuits
• Truth Table and Fault Matrix
Example:
 s-a-0 and 
s-a-1

x1
x2
x2
x3
x1
x3
&
&
1
z

&
Truth table approach not practical if
number of inputs is large.
x1 x2 x3
z
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
z z zz z z
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
Testing Sequential Circuits
• Testing of sequential circuits is harder than
combinational circuits
• Sequential Circuit Testing requires verification of
the state table
– Verify Reachability of all states
– Verify all transitions
• Assumption:
– Only the inputs and outputs are accessible, internal flipflops are not accessible
Testing Sequential Circuits
• Fortunately for us, ad-hoc testing techniques
(like scan-chains) has made the internal flip-flops
accessible, so the last assumption does not hold!
• In case access to internal flip-flops is too costly,
standard sequential test methods still have to be
applied, see Appendix.
Testing Sequential Circuits –
Scan-based Techniques
• Sequential Circuits have poor controllability and
poor observability
PI
Comb.
Part
PO
Comb.
Part
PI
PO
Scanout
Scanin
Full Scan and Partial Scan
• Full Scan:
– Connect all the storage elements to form a long shift
register (scan chain)
– The storage elements can be easily tested by shifting
in a pattern and observing the output
– Testing of sequential circuit testing can be now treated
as testing of combinational circuit
– Full scan is costly and slow
• Partial Scan
– Select a subset of storage elements to be included in
the scan chain
Random Access Scan
• To achieve controllability and observability of all registers
– Access one register at a time
PI
Comb.
Part
PO
Memory
Scan-in
Scan-out
Scan
Address
Board Level DFT: Boundary Scan
• Every input and output port of a chip is included in a
special scan chain
PI
Main Logic
SO
SI
PO
Test Data In
Test Clock
Test Mode
Test Data Out
Boundary Scan Cell
SO
PI
M
u
x
M
u
x
ClockDR
SI
UpdateDR
PO
JTAG Standard (IEEE 1149.1)
I/O Pad
Boundary-Scan cell
Boundary Scan-path
Summary of DfT
• Testing of complex digital systems is a hard but
very important task.
– Test Pattern Generation is most important in testing
• Testing contributes substantially to the cost and
effort required to design a new product.
• Methods are required to reduce this cost and
effort.
– Design for testability
– Reuse of proven designs
– Formal Methods
Test Pattern Generation - part I
Built-In Self Test (BIST) Methods
Testing a Circuit
Test Pattern
Generator
Circuit
Under Test
Response
Analyzer
Test Equipment
• Pulse and Function generators
• Oscilloscope
• Logic Analyzers
• Computers
• Specialized Zigs
+
Test Engineer
Self-Test a Circuit –
Built-In Self Test (BIST)
Test Pattern
Generator
Circuit
Under Test
Response
Analyzer
Package the test equipment
along with the circuit!
Test Engineer
BIST: Requirements
• Generation of Test patterns for testing
– DFT is very important
– Algorithm has to be very simple and easy to implement in
hardware
• Comparing Response
– It is not possible to store the response in memory: area overhead
– Related to Test Pattern Generation
• Compression of Test Patterns and Response is essential
for BIST design
Test Generation and Response
Compression
Input Test
Sequence T
Circuit
Under Test
Output
Response R
Test
Generator
Unit
Data
Compression
Unit
Correct
Signature
Signature S(R)
Comparator
Error
Indicator
General Aspects of Compression
• A simple hardware implementation
• It should not slow down normal operations
• Good Compression
– The signatures of good and faulty circuit should be
different
– Small size of signature. Signature size should be log of
data size.
• Issues:
– How to generate signatures for good circuit?
Generic Off-line BIST Architectures
• Classification
– Centralized or Distributed BIST circuitry
– Embedded or Separate BIST
• Key Elements of BIST
– Test pattern Generator (TPG)
– Output Response Analyzers (ORA)
– Circuit Under Test (CUT)
– A Distribution system for transmitting data from TPG to CUT and
from CUT to ORAs.
– A BIST Controller
Test Pattern Generation for BISTs
Exhaustive Testing

Exhaustive Test Pattern Generators
Pseudo-Random testing
 Weighted test generator
 Adaptive Test Generator
Pseudo-Exhaustive testing

Constant Weight Counter

Combined LFSR and Shift Register

Combined LFSR and XOR

Cyclic LFSR
Exhaustive Testing
• Apply all possible 2n test patterns to a n input circuit.
• A binary counter can be used
• Or a maximum length autonomous LFSR can be used
(add special circuit to generate all zeros).
• Normally applied when number of inputs are less than 25.
Pseudorandom Testing
• Patterns are generated deterministically but have
characteristics of random patterns.
• Pseudo-random patterns without replacement can be
generated using autonomous LFSRs.
• Test length can be chosen to achieve the desired fault
coverage. This can be determined using fault simulation.
• Limitation
– LFSR tend to produce patterns with equal numbers of 1’s and 0’s
– For some circuit it is better to bias the distribution of 0’s and 1’s of
the pattern generator. For example testing of AND requires more
1’s in the test pattern.
Weighted Test Generation
• Generate Test Patterns with the desired distribution of 1’s
and 0’s.
• Such a generator can be constructed using a LFSR and a
combinational circuit.
• Different parts of the circuit may require different
distribution of 0’s and 1’s.
Adaptive Test Generation
• Also employs weighted test pattern generation.
• Fault simulation is used to determine weights for various
faults.
• Different distributions are used for different class of faults.
• A Test Pattern Generator (TPG) is designed to produce
the required distributions.
• Advantage: Small test lengths
• Disadvantage: Costly TPG hardware
Pseudo-exhaustive Testing
• Requires fewer tests but has the advantage of exhaustive
testing.
• Segments the circuit into parts and each segment is
exhaustively tested.
• Logical Segmentation
– Cone Segmentation
– Sensitized path segmentation
• Physical Segmentation
Compression Methods for BISTs
Basic Idea – Apply sequence, check signature after finishing...
Simple Analyzers

Ones-count Compression

Transition-count Compression
Signature Analyzers
 Single-Input Signature Response (SISR)
 Multi-Input Signature Response Analyser (MISR)
Generic BIST architectures

BILBO
Ones-Count Compression
Assume a single output circuit C. Let the response of C to
a test sequence be R = r1, r2, ........., rm .In ones counting
the signature 1C(R) is the number of 1s appearing in R,
i.e.
1C(R) =  ri
where 0  1C(R)  m.
i
11110000
11001100
10101010
x1
x2
x3
&
X
s-a-1 f1
10000000
11000000
00000000
f2 s-a-0
X
&
z
R0
R1
R2
Ones Count Compression: Analysis
x1
x2
x3
Circuit
Counter
Signatures:
1C(R0) = 1
1C(R1) = 2
1C(R2) = 0
Clock
Masking Probability
The probability of an erroneous output sequence having the same number
of 1’s as the correct sequence.
Theorem: The masking probability for ones-count compression for a
combinational network circuit asymptotically approaches (m)-1/2.
Transition-Count Compression
The Transition Count signature is the number of 0-1 and
1-0 transitions in the output response sequence R. Let the
response of C to a test sequence be R = r1, r2, ........., rm.
In transition counting the signature TC(R) is
TC(R) =  (ri ri+1)
i=1
11110000
11001100
10101010
x1
x2
x3
&
X
s-a-1 f1
f2 s-a-0
X
&
10000000
11000000
00000000
z
R0 TC(R0)= 1
R1 TC(R1)= 1
R2 TC(R2)= 0
Transition Count Compression: Analysis
Transition
Detector
x1
x2
x3
Circuit
D
D
Q
Counter

Theorem: The masking probability for transition count compression for
a combinational network circuit asymptotically approaches (m)-1/2
Signature Analysis
+
0
•
1
1
S0
S1
S2
S3
S4
S5
S6
S7 =S0
0
0
1
0
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
0
1
0
1
1
Period of Linear Feed back shift register depends upon
– Feed back connections
– Intial value of register
• Masking probability is inversely related to the period
LFSR as a Single-Input Signature
Register (SISR)
Cn-2
Cn-1
Cn
+
D
+
Ci
Q
+
D
Q
+
C1
+
: Modulo-2 addition( an ex-or gate)
: If Ci=1 then there is a connection otherwise no connection
This Circuit can be used to compress the response with
masking probability = 2-n .
Multiple-Input Signature Registers
• Method 1: Time Multiplex the signature analyzer for each
output. That is repeat the test sequence for each
output.This will require long test time.
• Method 2: Use Multiple Input Signature Register (MISR).
D1
D2
D3
+
+
+
Cn
Cn-1
Cn-2
Error Masking Probability = 2-n
Dn
+
C1
Generic BIST Architectures
TPG
D
I
S
T
CUT
CUT
D
I
S
T
ORA
BIST
Controller
TPG
CUT
ORA
TPG
CUT
ORA
Build-In Logic Block Observer (BILBO)
• Motivation: It is difficult to self test a circuit which has a large number
of (Inputs+Outputs+Storage Cells).
– You require PRSG for inputs, MISR for outputs PRSG and MISR for
storage cells.
– Solution: Clustering of storage cells into registers and make these
registers carry out multiple jobs.
• BILBO is one such scheme.
– Registers can be configured for :
• Normal Operation
• As PRSG
• As MISR
• As Scan Register
BILBO Registers
X1
X2
Xn-1
D Q
D Q
Xn
B1
B2
Si
D
Q
EX
OR
B1
1
0
1
B2
1
0
0
Operation
Normal Operation
Shift Register mode
PRPG or MISR
D Q
EX
OR
So
BIST design with BILBO Registers
• Example:
R1
C1
To Test C1
•R1 as PRPG
•R2 as MISR
To Test C2
R2
C2
R3
•R2 as PRPG
•R3 as MISR
Summary of BIST
• BIST of a system requires techniques for
– Data Compression
– Test Pattern Generation
• Linear Feedback Shift Registers are good for doing both
• Important concerns
– Masking Probability
– Fault coverage
– Overhead
• Data Compression and Test Generation Functions can be
combined in one register (BILBOs)
Test Pattern Generation – part II
Automatic Test Pattern Generation
(ATPG)
Automatic Test Pattern Generation
(ATPG)
With Scan-chains available, deterministic tests are preferred.
Generic test method:
• Prepare a Fault list
• Repeat
– Write a test
– check fault cover (one test may cover more than 1 fault)
– delete covered faults from list
until fault cover target is reached or only un-testable faults remain.
ATPG Example
A
E
B
Z
C
D
F
• To test A/0 (A stuck-at-0), set A=1.
• To propagate A/0, set B=1
• To propagate result to Z, F must be 0
• Thus, Either C=0 or D=0 or C=D=0 are solutions (3 possibilities) => (110-,11-0)
• The test pattern (1101/0) is good because it also covers E/1, D/0, F/1 and Z/1
Boolean Derivatives
Traditional algebra: speed
Boolean algebra:
y = F(x)
y 0,1, F(X) 0,1
y
F ( X )
0
xk
F ( X )
0
xi
x
xi
xk
change
F ( X )
1
xi
F ( X )
0
xi
F(X) will change
if xi changes
F(X) will
not
change
if xi
changes
Boolean Derivatives
Boolean function:
Y = F(x) = F(x1, x2, … , xn)
Boolean partial derivative:
F ( X )
 F ( x1 ,...xi ,...xn )  F ( x1 ,...x i ,...xn )
xi
F ( X )
 F ( x1 ,...xi  0,...xn )  F ( x1 ,...xi  1,...xn )
xi
Example: Functional Description
Example:
F( x1, x2 ,x3) = x1x2+ x2x3+ x3x1
Fault: x1 stuck-at-1
F
 x x  (x  x  x x )
2 3
2
3
2 3
x1
= x2  x3
The function F will have different output, when
x2  x3 = 1, that is x2 =0 and x3 =1 OR
x2 = 1 and x3 = 0
Boolean Difference: Test pattern
generation
For a point Xi s-a-1
The solution of the equation
Xi
F
1
Xi
Gives all the tests for Xi stuck-at-1
For a point Xi s-a-0
The solution of the equation
F
Xi
1
Xi
Gives all the tests for Xi s-a-0
Boolean derivatives
Useful properties of Boolean derivatives:
 F ( X ) F ( X )

xi
xi
Test generation algorithm:
Solve the differential equation
F ( X ) F ( X )

xi
 xi
F ( X )
0
xi
F ( X )
1
xi
F ( X )
1
xi
if
F(x)
is independent of
xi
if
F(x)
depends always on
xi
Boolean derivatives
Useful properties of Boolean derivatives
If F(x) is independent of xi
F ( X )G( X )
G( X )
 F(X )
xi
xi
F ( X )  G( X )
G( X )
 F(X )
xi
xi
These properties allow to simplify the Boolean differential equation
to be solved for generating test pattern for a fault at
xi
Boolean derivatives
Given:
y  x1x2  x3 ( x5  x2 x6 )
Calculation of the Boolean Difference w.r.t. x5
 ( x3 ( x5  x2 x6 ))
y
 x1 x2
x5
x5
 ((x5  x2 x6 )))
 x1 x2 x3
x5
x5
 x1 x2 x3 x2 x6
x5
 x1 x2 x3 x2 x6
A Complete Test: Intermediate circuit
points must also be tested
Example
A
B
&
B
C
&
C
A
F  BC  CA  h
h s-a-1
&
&
 A B  C
Test for h s-a-1
h
F
1
h
F
F
 1  ( BC  CA)
h
 BC  CA
 AB( A  B  C)  1
 ABC = 1
A = 1; B= 1; C= 0.
Example: Complete Test using
Boolean Derivatives
A
B
C
D
Z  E  F  AB  CD
E
Z
F
Z
 ( AB)
 CD
 CDB  (C  D)B
A
A
Z
 ( AB)
 CD
 CD A  (C  D) A
B
B
Z
 (CD )
 AB
 ABD
C
C
Z
 (CD )
 AB
 ABC
D
D
Z
 F  CD  (C  D)
E
Z
 E  AB
F
E  AB
F  CD
Z
Z
 AB(C  D) , A
 AB(C  D)
A
A
Z
Z
B
 AB(C  D) , B
 AB(C  D)
B
B
Z
Z
C
 ABCD
, C
 ABC D
C
C
Z
Z
D
 ABCD
, D
 ABCD
D
D
Z
Z
E
 ( A  B)(C  D) , E
 AB(C  D)
E
E
Z
Z
F
 ABCD
, F
 ABCD  AB(C  D)
F
F
A
Fault Cover Check
Test Pattern
A
Sa0
B
Sa1
Sa0
C
Sa1
Sa0
D
Sa1
Sa0
E
Sa1
Sa0
F
Sa1
Sa0
Z
Sa1
0000
X
X
0001
X
X
0010
X
X
0011
One of
these
Sa0
X
1000
Redundant
X
X
X
X
0101
Redundant
X
X
X
X
0110
Redundant
X
X
X
X
0111
X
1000
X
X
1001
X
X
1010
X
X
1011
X
1100
1101
Essential
1110
1111
Sa1
Essential
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Path Sensitization
The method consists of two steps:
– Identify a sensitized path from the fault site to output
– Check for consistency of the assignments to the inputs
Example Circuit
1
1
X1
X2
0 X3
X X4
X X5
X X6
G1
7
S-a-0
&
G2
10
&

13
1/0
0
G7
8
G4
9
15
&
&
G3
G5
11
1
12
X
G6

14
1
1
1/0
Good value
Bad value
Path Sensitization
Node
1
2
G1
1
1
3
4
5
6
7
8 9
11
12 13
1
1
1/0
0
0
X
G6
X
G3
G2
1
1
15
1
1/0
1
1/0
1/0
0
G7
G4
14
1/0
G5
Gates
10
0
X
0
X
X
X
X
1
1/0
1
1
X
1/0
0
0
0
0 X
0
0
1
1/0
1
1/0
Path Sensitization: Sensitization of
multiple paths
Example: Fault 6 s-a-0
G4
G1
1
X1
1
5
0
1
0 X2
0 X3
X4
2
3
G2
1
G5
1
9
0
0/1
0
10
0
6
1/0
4
1
G3
1
8
7
0
G6
1
G7
1
1
11
G8
1
1/0
12
Path Sensitization: Sensitization of
multiple paths
Example (Continued)
G4
G1
1
X1
0 X2
2
0 X3
3
X4
4
1
5
0
1
G2
1
G5
1
0
7
1
G6
1
G7
1
0
0
9
0/1
6
1/0
G3
1
8
10
11
G8
1
0/1
0
1/0
12
D-Algorithm
The ideas of Path sensitization method are
formalized.
D-Notation
The signal can take value from the set { 0,1,x,D,D }
Faulty Circuit
0
1
Good
Circuit
0
0
D
1
D
1
Singular Cover
Singular Cube is a compact representation of the truth
table of a component.
Example: 2-input AND gate
Singular Cover
Truth Table
A B
C
0
0
0
0
1
0
1
0
0
1
1
1
A
B
C
0
x
0
x
0
0
1
1
1
Primitive D-Cube
Model of the component in the presence of fault.
Example: 2-input NOR gate
Fault
Primitive D-Cube
A
B
C
A s-a-0
A s-a-1
C s-a-0
1
0
0
0
0
0
D
C s-a-1
1
X
X D
1 D
D
D
A
B
1
C
Propagation D-Cube
• Model of a good component in a faulty circuit.
• Must propagate the fault from the inputs to one of
the outputs.
Example: 2-input NOR gate
A
B
C
D
0
D
0
D
D
D
D
D
-------------------------------
D
0
0
D
D
D
D
D
D
D-intersection
• This is a method to propagate fault from the
component to the output and to make consistency
check.
1 2 3 4 5
Example
X1
1
X2
2
X3
Primitive D-Cube
G1

4
3
Fault Node 2 s-a-0
Propagation D-Cube
G2

5
Z
Cube Intersection
0
1
x
D
x
x
x
D D
0
1
0
0
D D
D-Algorithm: Forward Drive
X1
1
X2
2
X3
X4
3
4
G1

x
D
Propog. D-Cube
G4 0
D
G5 1
D
G3
&
7
G5
9
&
G2
8
G4
&

6
Primitive D-Cube
of Fault
G2 0
5
1
2
G2
G4
0

0
3
4
0
x
5
6
x
D

0
0
x
9
D
D
0
8
D
D
G5
D
7
D
1
D
D
D
1
D
D
D-Algorithm: Consistency Check
1
Singular Cover
G3 0 x
1
G1 1 x
0
2
3
4
0
0
x
G3
0

0
G1
1
x

1
0
0
5
6
7
D
1
x
x
x
8
9
D
D
1
D
1
D
1
D
D
0
0
x
0
D
D
Re-convergent Fanout
• Example: Point 6 s-a-0
G4
G1
1
X1
5
X2
2
X3
3
X4
4
1
G5
1
1
G2
1
9
G8
1
6
1/0
G3
1
8
7
G6
1
G7
1
10
11
12
D-Algorithm: Sensitizing Multiple Paths
X1
X3 X4
5
0 0
G2
G5&G6
X2
0
6
7
0
D
0
0 0 0 0
0
G4
G1
G3
D
0
10
11
12
D
D
1
0
D
D
0
D
D
D
0
D
0
1
0
0
0
1
0
G7
9
D
G8

8
1
0
D-Algorithm: Worst Case and Time
Complexity
• In the worst case the D-Algorithm will have to consider all
combinations of path.
• In a circuit with N components, the number of
combinations of paths from fault to output are: k2N.
• Worst case time complexity of D-Algorithm: O(2N).
• Fortunately, in practice average time complexity is much
smaller (N2).
– If size of circuit grows by 10, number of tests required grows by
100.
Appendix
Testing Sequential Circuits
Testing Sequential Circuits
• Testing of sequential circuits is harder than
combinational circuits
• Sequential Circuit Testing requires verification of
the state table
– Verify Reachability of all states
– Verify all transitions
• Assumption:
– Only the inputs and outputs are accessible, internal flipflops are not accessible
Case Study Example
Example 1
1/0
Pattern
Detector (0110)
X
S0
0/0
Z
S1
0/0
0/0
1/0
S2
State X= 0 X= 1
S0
S1
S2
S3
S1,0
S1,0
S1,0
S0,1
S0,0
S2,0
S3,0
S0,0
0/1
1/0
S3
1/0
Homing Sequence
Def.: Smallest input sequence which brings the
machine to a known state.
{S0,S1,S2,S3}
0
{S1,S1,S1,S3}
0
{S1,S1,S1,S1}
1
{S0,S2,S3,S0}
1
{S2,S2,S2,S0}
Therefore ‘00’ is the homing sequence for the machine
Distinguishing Sequence
Definition: Smallest input sequence which
produces a different output for each starting state.
Example 2: mod-4 counter
X
Mod-4 counter
State X= 0 X= 1
S0
S1
S2
S3
S0,0
S1,0
S2,0
S3,0
S1,0
S2,0
S3,0
S0,1
Z
• Example 1 does not have a common
distinguishing sequence for all states.
• The common distinguishing sequence for
Example 2 is ’1111’.
S0
Output = 0001
S1
Output = 0010
S2
Output = 0100
S3
Output = 1000
Transfer Sequence
Definition: Smallest input sequence which takes
the machine from state i to state j, for all states i
and j.
Example 1:
Example 2:
i
j
Sequence
S0
S0
S0
S1
S1
S1
S2
S2
S2
S1
S2
S3
S0
S2
S3
S0
S1
S3
0
01
001
110
1
11
10
0
1
i
j
S0
S0
S0
S1
S1
S1
S2
S2
S2
S1
S2
S3
S0
S2
S3
S0
S1
S3
Sequence
1
11
111
111
1
11
11
111
1
Checking Experiment: Steps
Steps:
1. Go to a known starting state by using a homing
sequence or a distinguishing sequence.
2. Check reachability of all the states
3. Check all transitions
Checking Experiment: Step 1
Known Initial State
Example 1
Homing Sequence: 00
Known State : S1
Example 2
Distinguishing Sequence: 1 1 1 1
Final State : If output = 0001 then S0
else if output = 0010 then S1
else if output = 0100 then S2
else S3;
Checking Experiment: Step2
Check reachability of all states
Example 2:
Known Intial State : say S1
Check reachability to S2
Give transfer sequence for S1 to S2, that is, 1
Distinguish S2 by distinguishing sequence 1111:
Output should be 0100 and final state S2.
Check reachability to S3
Give transfer sequence for S2 to S3, that is, 1
Distinguish S3 by distinguishing sequence 1111
Output should be 1000 and final state S3
Check reachability to S0
Checking Experiment: Step3
Check various transitions
Example 2:
Present State = S0
Check transition ( S0,0)  S0/0
Give 0 and check output to be 0
To check next state as S0 give distinguishing sequence 1111 and
check output to be 0001.
Check transition ( S0,1)  S1/0
Give 1 and check output to be 0
To check next state as S1 give distinguishing sequence 1111 and
check output to be 0010.
Similarly all other transitions.