On-Chip Reliability Monitor for Measuring Frequency
Degradation of Digital Circuits
By
Han Lin
Jiun-Yi Lin
Department of Electrical and Computer Engineering
05/14/2014
Overview
 Introduction
 Principle and background
 Proposed reliability monitor circuit
 Circuit Blocks and Simulation Result:
 Ring Oscillator
 Phase Comparator
 Majority Voting Circuit
 Beat Frequency Detector
 8 Bit Counter Circuit
 Total Circuit
 Conclusion
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Abstract
Precise measurement of digital circuit degradation caused
by aging
Reliability monitor using beat frequency of two ring
oscillators to get a high sensing resolution
1V, 32nm CMOS technology, up to 0.02% sensing
resolution
Overview
 Introduction
 Principle and background
 Proposed reliability monitor circuit
 Circuit Blocks and Simulation Result:
 Ring Oscillator
 Phase Comparator
 Majority Voting Circuit
 Beat Frequency Detector
 8 Bit Counter Circuit
 Total Circuit
 Conclusion
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Types of reliability issues
BTI (bias temperature instability)
HCI (hot carrier injection)
TDDB (time-dependent dielectric breakdown)
NBTI (negative bias temperature instability)
NBTI effect is among the most pressing issues among all of
them
Cause of NBTI effect
Structural mismatch at the Si-SiO2 interface cause dangling bonds
Si-H bonds is transformed by hydrogen passivation process of dangling
Si bonds which is made by oxidation of Si-SiO2
Broken bonds from Si-H degrade the driving current of pMOS threshold
voltage
Positive shift in absolute value of pMOS threshold voltage |Vtp| in
stress phase
Broken Si-H bonds is annealed in recovery phase, and Vtp is reduced
Cross section of pMOS device and pMOS Vth degradation
Constraints of typical measurement
Device probing, on-chip ring oscillator frequency monitoring
Limitations in sensing resolution, cannot get large number
of data points
Simulation platform
Microsoft Windows
HSPICE 2009
CosmosScope
Overview
 Introduction
 Principle and background
 Proposed reliability monitor circuit
 Circuit Blocks and Simulation Result:
 Ring Oscillator
 Phase Comparator
 Majority Voting Circuit
 Beat Frequency Detector
 8 Bit Counter Circuit
 Total Circuit
 Conclusion
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Beat frequency detection circuit
Measuring difference in frequency between Stressed and
Reference ROSC
When there is exactly one in the
pulse difference between two
ROSC, we can get the value of N
before stress, and we use this
method to get N’ which is detected
after stress period.
Beat frequency detection scheme
Using difference between stressed and reference ROSC
Before stress: N/fref=(N-1)/fstress
After stress: N’/fref=(N’-1)/f’stress
Percent of frequency degradation:
(f’stress-fstress)/fstress=(N’-N)/(N’(N-1))
Change in counter output by frequency degradation
(f’stress-fstress)/fstress
=(N’-N)/(N’(N-1))
When there is 1%
degradation, N will
decrease half compared
with 1% for convention
method
Architecture of silicon odometer
Two ring oscillators, identical structure, different Vdd
Phase comparator will show frequency difference between
two ROSC.
5-bit majority voting circuit can erase the bubbles caused
by jitter effect from phase comparator
Beat frequency detector can produce a DETECT signal to
reset the counter, and get the output from the register
Block diagram
Overview
 Introduction
 Principle and background
 Proposed reliability monitor circuit
 Circuit Blocks and Simulation Result:
 Ring Oscillator
 Phase Comparator
 Majority Voting Circuit
 Beat Frequency Detector
 8 Bit Counter Circuit
 Total Circuit
 Conclusion
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Ring Oscillator
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Simulation Result of Ring Oscillator Circuit
 The ring oscillator has a period of 4 ns
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Phase Comparator
X: Pre charge
Switch close
Switch open Switch close
 CLK=0 Pre charge
 CLK=1 Evaluate
(Compare the phase of A
and B)
CLK=1
CLK=0
A’&&B=1
PC_OUT keep
PC_OUT=1 the same value
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CLK=1
A’&&B=0
PC_OUT=0
5
Simulation Result of Phase Comparator Circuit
CLK=1
A’&&B=1
PC_OUT=1
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CLK=0
PC_OUT keep
the same value
CLK=1
A’&&B=0
PC_OUT=0
6
Majority Voting Circuit
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Majority Voting circuit (Continue)
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Simulation Result of Majority Voting Circuit
PC_OUT
10111010
10111011
VOTE_OUT
11111100
111111 00
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Beat Frequency Detector
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Simulation Result of Beat Frequency Detector Circuit
Beat Frequency
Latency
111111 00
10111 011
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8 Bit Counter Circuit
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Simulation Result of 8 Bit Counter
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Simulation Result of Total Circuit
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CONCLUSION
■
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THANK YOU!
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