Hi-Rel Operations
2010
August 2008
National – A Global Company
South Portland, ME
Santa Clara, CA
Finland
Scotland Estonia
Netherlands
Germany
Italy
India
Japan
Korea
China
Taiwan
Malaysia
Wafer Fabs
World Headquarters
– Santa Clara, California, US
Regional Business Divisions
– Americas
– Europe
– Japan
– Asia Pacific
Design Centers
– South Portland, Maine USA – United States (15)
– Greenock, Scotland
– Scotland
– The Netherlands
Assembly Plants
– Germany
– Santa Clara, Ca USA
– Italy
– Melaka, Malaysia
– India
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
–
–
–
–
–
–
China
Taiwan
Japan
Finland
Estonia
Korea
August 2008
World-Class Manufacturing
Our Strategic Asset
• Greenock, Scotland – 6in
– Leading-edge analog Bipolar, BiCmos + Dmos,
CMOS processes
• South Portland, Maine – 8in
– Advanced CMOS /
BiCMOS (SiGe and SOI) processes
– Running advanced analog
– US Secure Foundry
• Santa Clara, USA and Melaka, Malaysia
– Custom Hermetic Package Design
– Test & Assembly
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Hi Rel Operations
August 2008
National Semiconductor
– A Rich Space Analog Portfolio
Analog Building Blocks
QMLV Qualified Products
30+ Years in the Space Market
• State of the art radiation tolerant process technology (ELDRS Free)
• Industry leading hermetic package technology
• Renewed focus on Technology Driven Analog Solution
• Radiation Testing: SEL, SEU & TID Reports
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Hi-Rel Operations Customer
Support and Documentation
• Customer
Communications
– Quarterly News Letter
– Customer Portals
• Radiation Reports
TID
SEU/SET
• Ceramic Eval Boards
SEL
National Semiconductor
Hi-Rel Operations Radiation Engineering/RHA Programs
2900 Semiconductor Drive
Santa Clara, CA 95052
– Hi-Rel Web Site
Single Event Effect Report
Micro Power
12 b Digital to Analog Converter
www.national.com/space
LM98640CVAL
DAC121S101WGMLS
DAC121S101WGRQV
(5962R0722601VZA)
ADC10D1000CVAL
Date: November 17, 2008
Rev: B
Principle Investigator and Editor: Kirby Kruckmeyer
+1 (408) 721-3548
Kirby.Kruckmeyer@nsc.com
Written By: Sandeepan DasGupta (Product Engineer Intern)
ADC14155HCVAL
ADC14155LCVAL
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
ADC08D1520CVAL
August 2008
Die Products at National
• WAFER
– Whole wafers
in vials
• DICED
–
–
–
–
Waffle Pack
GEL-PAK®
Tape on Reel
Wafer on
film frame
• Die Products contact
– See web site for
information
• Web
– www.national.com/die
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Hi-Rel Focused Satellite Strategy
Work with our customers to help solve system challenges
by developing leading edge Analog Solutions enabling
innovative and successful missions.
1. Enhanced Heritage Products
2. Aggressively pursue the satellite market with high
performance fully QMLV qualified analog products
ELDRS
AOCS
Communication
Wide
Band
Space Imaging
Power
Narrow
Band
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
High and Low Dose Rate Improvements
- legacy Portfolio
What is ELDRS and Why is It Important?
Enhanced Low Dose Rate Sensitivity:
An increase degradation
in electrical performance between low dose rate and high dose rate.
• Many bipolar linear circuits are used in space systems and many suffer
from ELDRS
• System performance may be degraded by ELDRS
• It is hard to identify system malfunctions related to ELDRS
– “Failures” are usually parametric and not functional
– Design margins are often high
– Circuits are often not “suspect” if they passed ground test at HDR
• ELDRS has been demonstrated in space (See papers from NSREC &
RADECS)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ELDRS-Free Products!
• We test them so you don’t have to!
• Every wafer tested and qualified at low
dose rates
– per Mil-Std-883 method 1019 condition A&D
– Low dose rate of 10 mrad/s (36 rad/hr)
– Biased and unbiased
• DSCC unique low dose rate certified part
numbers
ELDRS-Free LM139
• ELDRS Free Products
LM111
LM139
LM119
LM117
LM158
LM2941
LM124
LM136-2.5
LM193
LM7171
LMP2012
•Products in Qualification
LM101
LM2940
LM137
LM113
• Low Dose Rate Qualified
LM117HV
Also available in die form
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
High Dose Rate Improvements
- on Legacy Products
Continue to work on radiation performance for existing devices
• Radiation process developed to improve total dose
performance
Before
Today
– LM137
10krad
30krad
– LF411
10krad
50krad
– LM101
10krad
50krad
– LM111
10krad
50krad
– LM136
10krad
100krad
– LM158
10krad
100krad
– LM124
10krad
100krad
– LM139
10krad
100krad
– LM117
10krad
100krad
– LM117HV
3krad
100krad
– LP2953
10krad
In Progress
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Hi-Rel Focused
New Product Development
Space
Imaging
Applications
AOCS
Power
Communication
System Function
Maintain or Change
Orbit
Payload & Bus
Backbone of
Communications Market
Integral in National
Security and
Tracking
System
Requirements
Lower Power,
Increase
Precision
Higher Efficiency, <1.2V,
Faster Response Time,
High Currents
Higher Bandwidth,
Lower Noise Power
Ratio, Lower Power
Lower Power,
Higher Resolution,
More Integration
1 MSPS ADC &
DACs
LDOS
High Speed & Giga Sample
ADCs
Low Power Analog
Front Ends
Products
Developed
Precision Amps
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC128S102WGRQV -
QMLV Available today!
8-Channel, 12-Bit, 50 KSPS to 1MSPS, General Purpose ADC
– Only 2.3mW of Power
•
0.06 uW in Power Down
– Eight Input Channels
– DNL – -0.2 to +0.4 LSB typical
– INL – +/- 0.4 LSB typical
– Split Supplies
•
VA 2.7V to 5.25V
•
VD 2.7V to VA
– SPI Digital Output
– 16ld Gull Wing Ceramic Cerpac
– Space Level Version
•
TID of 100 krad(Si)
•
Single Event Latchup > 120 MeV
50 KSPS
1 MSPS
– Order as 5962R0722701VZA
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC128S102WGRQV Specifications
SPECIFICATION
Resolution
Input Channels
Sampling Rate
Voltage Supply
ADC128S102WGRQV
12 bits
8
50 KSPS to 1MSPS
+2.7V to +5.25V
Input Range
Reference
Output Data Format
Guaranteed No Missing Codes
0 to VA
Internal
SPI, QSPI, Microwire, DSP Interfaces
4096 Codes
-0.7 to + 0.9 LSB (max)
@VA =VD=3.0V
DNL
INL
+/- 1.0 LSB (max) @V A =VD=3.0V
SNR
SINAD
ENOB
THD
SFDR
Offset Error
73 dB (typ)
73 dB (typ)
11.8 bits (typ)
-90 dB (typ)
92 dB (typ)
+/-2.3 LSB (max)
Gain Error
+/- 2.0 LSB (max)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
• Std Ceramic package
WG16A
• 8 Channels in only 16 pins
– Reduces board space
and weight
– Reduces PCB traces
and cabling
August 2008
DAC121S101WGRQV -
QMLV Available Now!
12-Bit Micro Power General Purpose DAC with Rail-to-Rail Output
– Only 0.64mW of Power
•
Vcc
0.14 uW in Power Down
– Supply range of +2.7V to +5.5V
– Guaranteed Monotonic
Din
Sclk
Snyc
– DNL +0.25/-0.15 LSB
Vout
Gnd
– 3-wire 20MHz SPI Digital Interface
– Settling Time 12μS
– Hermetic 10ld Gull Wing Ceramic Cerpac
– Space Level Version
•
TID of 100 krad(Si)
•
Single Event Latchup > 120 MeV
– Order as 5962R0722601VZA
1001011001101
0101001101001
1001011001101
0101001101001
1001011001101
0101001101001
1001011001101
0101001101001
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
DAC121S101WGRQV Specifications
SPECIFICATION
Resolution
Input Data Format
Input Rate
Voltage Supply Range
Output Range
Reference
DNL
Output Settling Time
Full-Scale Error
Gain Error
DAC121S101WGRQV
12 bits
SPI, QSPI, Microwire, DSP Interface
20 MHz
+2.7V to +5.5V
Rail-to-Rail
Internal
-0.15 to + 0.25 LSB (max)
12 us
-0.06 %FSR (max)
-0.10 %FSR
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
• Std Ceramic package WG10A
• Serial interface
–
Allows for small 10 pin
package
–
Reduces package footprint
and weight
–
Reduces PCB traces and
cabling
August 2008
LMP2012WGLQMLV -
QMLV Available!
Dual Channel, High Precision, Railto-Rail Output Op Amp
–
–
–
–
–
–
–
–
–
–
–
Very Low TCVOS – 0.015uV/°C
Low Input offset voltage of 60 μV over time
and temperature.
No 1/f noise - input-referred voltage noise
of 35 nV/ Hz
Low supply current – 920uA
Wide gain bandwidth – 3MHz
2.7 to 5.0V supply voltage range
High CMRR – 130 dB
High PSRR – 120 dB
Hermetic 10-pin ceramic gullwing flat
package
Space Level version
•
TID of 50 krad(Si)
•
ELDRS qualified to 50 krad(Si)
•
Low SET Cross-Section
Order as 5962L062061VZA
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
No 1/f Noise
Input-Referred Voltage Noise of 35 nV/ Hz
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Offset Voltage
-
Over Supply and Temperature
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
LM2941QML ELDRs Free 1A LDO
Available!
• Features
– 1A Adjustable Regulator
– Adjustable Output Voltage 5V-20V
– Input Voltage up to 26V
– Input protection up to -15V
– Drop Out Voltage 0.5V
– Quiescent Current 10mA
– On / Off Pin
– Internal short circuit current
protection
– ELDRs Free up to 100krad/si
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC14155 -
Space Qualified Available Today!
14-bit 155 MSPS ADC
Input bandwidth of 1.1GHz
–
11.3 ENOBs at fin=70 MHz, 11 ENOBs at fin=169MHz
–
SNR of 70.1 dB at fin=70 MHz, 68.5 dB at fin=169MHz
–
SFDR of 82.3 dB at fin=70 MHz, 80.5 dB at
fin=169MHz
–
Power Consumption of 967mW at 155 MSPS
–
Guaranteed no missing codes
–
Dual 1.8V and 3.3V operation
–
In 48 pin Hermetic Ceramic Quad Flat Pack
–
Space Level Version
•
TID of 100 krad(Si)
•
Single Event Latchup > 120 MeV
VCO
–
RF
PLL
BPF
LMH6517
ADC14155
BPF
LMH6517
ADC14155
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
National vs. Competition
Part
Resolution (bits)
Speed (MSPS)
Power Consumption
ENOB (Bits)
SNR (dB)
SFDR (dB)
Analog BW
SEL
ADC14155QML
14
155
967mW
11.5
69 at 240 MHz
77 at 240 MHz
1.1 GHz
SEL >120MeV
XXXX
14
105
1.9W
10.2
63 at 230 MHz
64 at 230 MHz
570 MHz
SEL>60MeV
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
XXXX
14
80
1.75W
10.1
72 at 200 MHz
63.5 at 200 MHz
270 MHz
August 2008
ADC14155
ENOB vs. Temperature
11.900
ENOB (bits)
11.700
11.500
11.300
11.100
10.900
10.700
10.500
-60 -50 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Temperature deg. C
socketed device Fs=100MHz, Fin=70MHz, ENOB
soldered device Fs=100MHz, Fin=70MHz, ENOB
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC14155
SFDR vs. Temperature
95.000
SFDR (dBFS)
90.000
85.000
80.000
75.000
70.000
65.000
60.000
-60 -50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Temperature deg. C
socketed device Fs=100MHz, Fin=70MHz, SFDR
soldered device Fs=100MHz, Fin=70MHz, SFDR
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC14155
SINAD vs. Temperature
73.000
72.000
SINAD (dBFS)
71.000
70.000
69.000
68.000
67.000
66.000
65.000
-60 -50 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Temperature deg. C
socketed device Fs=100MHz, Fin=70MHz, SINAD
soldered device Fs=100MHz, Fin=70MHz, SINAD
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC14155
Power vs. Sampling Rate
ADC14155 Power vs. Sampling Rate
1000
950
y = 1.4916x + 704.39
Power (mW)
900
850
800
750
700
30
40
50
60
70
80
90
100
110
120
130
140
150
160
Sam pling Rate (MSPS)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC08D1520WGFQV -
QMLV Available!
• Dual Channel 8-Bit 1.5 GSPS ADC, Single
8-bit 3 GSPS ADC
–
–
–
–
–
–
–
–
–
–
Max sampling frequency 1.7GSPS
Inputs may be interleaved to obtain a 3GSPS
single ADC
Input bandwidth of 2 GHz
7.2 ENOBs out to Nyquist
Lowest Power in the industry at 1 W per channel
at 1.5 GSPS from single 1.9V supply
Very low cross-talk (-66 dB @ 1160 MHz)
Low-noise deMUX’d LVDS outputs
Guaranteed no missing codes
In 128 pin Hermetic Ceramic Quad Flat Pack
Space Level Version
•
•
–
TID of 300 krad(Si)
Single Event Latchup > 120 Mev
Order as 5962F0721401VZC
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
128-Lead Ceramic Quad (Gold Lead Finish)
NS Package Number EL128A
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC08D1520WGFQV ENOB vs. Clock Freq,
Input Frequency 248.47MHz versus Temperature.
Bench @ Room and Hot
8
ENOB
7
6
5
Hot
4
Room
3
2
-100 100 300 500 700 900 1100 1300 1500 1700 1900 2100
Clock Frequency (MHz)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Bench FFT , Sample Rate = 1500Mhz ,
Input 397.47MHz I Channel
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Bench FFT , Sample Rate = 1500Mhz ,
Input 797.47MHz I Channel
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Bench FFT , Sample Rate = 1500Mhz ,
Input 997.47MHz I Channel
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Bench FFT , Sample Rate = 1500Mhz , Input
1597.47MHz I Channel
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Dynamic vs. Temperature
ADC08D1520WGFQV with and without Cal
1.0 GSPS Clk +1.0dBm, 247.97Mhz +3.6dBm I/F Non-SPI Mode,
FS=1(870mV pk-pk) Note: The Input Amplitude is held constant over
the temperature range.
7.8
Calibration performed at every Temperature
Change.
ENOB
7.6
7.4
Key Points: Calibration was performed only
upon Pwr up. Then Cal was performed
again after last temperature sweep.
7.2
7
25
35
45
55
65
75
85
Ambient Temperature ('C)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
GiG Evaluation System
- Enable complete system demo for customers
• NSC’s ceramic evaluation board interfaces to a PC through the USB
interface.
• National uses a Xilinx Virtex-4 processor for the data capture.
• National also supplies the wavevision software for data analysis.
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC10D1000QML -
Space Qualified Available Today!
Dual Channel 10-Bit 1GSPS ADC, Single 10-bit 2 GSPS ADC
–
Full Power Bandwidth of 2.8 GHz
–
9.0 ENOBs @ Fin 249MHz Fs – 1.0GHz
8.9 ENOBs @ Fin 498MHz Fs – 1.0GHz
–
56.1dBc SNR @ Fin 249HMz Fs- 1.0GHz
56.8dBc SNR @ Fin 498HMz Fs- 1.0GHz
–
62.1dBc SFDR @ Fin 249MHz Fs – 1.0GHz
62dBc SFDR @ Fin 498MHz Fs – 1.0GHz
–
Lowest Power in the industry at 1.45 W per channel at
1GSPS from single 1.9V supply
–
Inputs may be interleaved to obtain a 2 GSPS single
ADC
–
Very low cross-talk (-61 dB @ 497 MHz)
–
Low-noise deMUX’d LVDS outputs
–
Guaranteed no missing codes
–
In 376 pin Hermetic Ceramic Column Grid Array Package
–
Space Level Version
•
TID of 100 krad(Si)
•
Single Event Latchup > 120 MeV
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
National vs. Competition
Part
Resolution (bits)
Number of Channels
Sample Rate
Supply
DNL
Power/Channel
Full Power Bandwidth
Single Event Latchup
ADC10D1000QML
10
2
1 GSPS, 2GSPS
1.9V
+/-0.2 LSB
1.45W
2.8 GHz
SEL >120MeV
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
XXXXXX
12
1
500 MSPS
5V & 3.3V
+/-1 LSB
2.2W
1GHz
SEL ~63MeV
August 2008
Simplified Functional Block Diagram
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ENOB vs. Fin
ENOB
I Chan, Ceramic Package @ room, Fclk = 1 GHz
QChan, Ceramic Package @ room Fclk = 1 GHz
9.6
9.3
9
8.7
8.4
8.1
7.8
7.5
7.2
6.9
6.6
90
290
490
690
890
1090
1290
1490
1690
1890
2090
Input Frequency
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
SFDR
vs. Fin
I and
Q Channel
(dBc).
SFDR (dB)
I Chan, Ceramic Package @ room Fclk = 1 GHz
QChan, Ceramic Package @ room Fclk = 1 GHz
80
75
70
65
60
55
50
45
40
35
90
290
490
690
890
1090
1290
1490
1690
1890
2090
Input Frequency
August 2008
NPR vs. Notch Width
• The NPR was measured at
each notch width and the
average is shown.
NPR vs. Notch Width
49.00
• At fc,notch = 320MHz,
f=250MHz is never included
for all notch widths.
NPR [dB]
48.50
48.00
NPR
47.50
47.00
0
5
10
15
Width [%]
• The measurement
stabilizes after about 4%,
so a 5% notch width
(25MHz, ~750 bins) was
chosen for most
measurements.
• After 10%, the NPR begins
to degrade.
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC10D1000QML Power
• Power vs Clock Frequency @ Room
1.9
1.8
Power/Channel (W)
1.7
1.6
1.5
1.4
ADC10D1000QML
1.3
1.2
1.1
Sample Rate (MSPS)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC10D1000QML ENOB vs. fCLK
I Channel, LFS = Low
I Channel, LFS = High
Writing the LFS bit High improves performance at fCLK = 100 MHz.
LFS doubles the charge pump frequency improving performance with low fCLK.
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC10D1000QML Auto-Sync Feature
• The ADC10D1000QML has an auto-sync mode for continuous
synchronization of an arbitrary number of ADCs in a system
• A Master-Slave configuration for the subdivision of the
converter clock, CLK, to the slower DCLK output is used
to ADC #8
to ADC #9
RCLK1
ADC #4
RCLK2
D1<1:10>
AutoSync
VIN
CLK
RCLK_IN
to ADC #5
TCLK
RCLK1
DCLK
D2<1:10>
ADC #2
TDCLK =
4 x TCLK
RCLK2
D1<1:10>
AutoSync
VIN
CLK
RCLK_IN
DCLK
D2<1:10>
from ADC #1
(Master)
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
376 Column Grid Array Package
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
376 Column Grid Array Package
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Columns from 6Sigma
Copper
Ribbon
•
•
•
•
Column Core Material: 80Pb/20Sn
Column Diameter: 20mils
Column Height: 87mils
Column Core wrapped with Copper Ribbon
and eutectic solder coating of 37Pb/63Sn
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
National’s 376 Column Grid Array
- Temperature Cycle Board
• Experiment between standard 80Pb/20Sn Copper
Ribbon Columns
• Daisy Chain Test Chip
10Min Dwell
125°
C
36°C/Min
1.5min 11.5min
16.5min
26.5min
0°C
13min
30min
Time
-55°C
10Min Dwell
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC10D1000 Reinforced Copper Columns
after 3000cycles
3000 cycles 80Pb/20Sn
3000 cycles 80Pb/20Sn
3000 cycles 80Pb/20Sn
3000 cycles 80Pb/20Sn
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
ADC10D1000 SEE Testing Results
• No SEL up to 120MeV
• No SEFI up to 120MeV
• SEU for DCLK
– Outage Time: 0.02ps/month
– Clock Upsets: 2.2X10-5 events/month
– Longest Event: typically 1 clock cycle
• SEU Code Error Rate
– Outage Time: 0.1ns/ch/month
– Data Upsets: 1.8X10-3
events/ch/month
– Longest Event: 55ns
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Weibull Plots for DCLK
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
Weibull Plot for Code Error / Channel
NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008
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NATIONAL SEMICONDUCTOR CORPORATION CONFIDENTIAL
© 2008 National Semiconductor Corporation. All Rights Reserved.
August 2008