L26 – Datapath ALU
implementation
Datapath ALU
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The full ALU
Incorporating ALU into datapath
From Datapath to microprocessor
Ref: text and basic computer architecture
books
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The full ALU
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ALU does both arithmetic and logic
operations.
For the logic operations use a 4-to-1
multiplexer and ALU can do any logic
operation on two bits.
Arithmetic operations are add (no carry), add
with carry, subtract (2’s complement),
subtract with borrow, increment, and
decrement.
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The structure
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The internal ALU structure
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Incorporating into datapath
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Take ALU
component, add input
registers and output
bus driver
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How to approach this in quartis
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Have the register set.
Build up the ALU unit
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But how to build up the ALU unit?
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Assignment HW 12 – Create the core of the ALU unit – an
add unit, a logic unit (4-to-1 mux), the 2-to-1 Mux for
selecting the output from which unit, and the internal
controller. Note that there will be several interface signals
to the units.
MUX – the function control signals (4), A, B
Adder – A,B, the carry in
OUTPUT Mux – L, R, select
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Assignment HW12
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Create the blocks
Create the core unit
Synthesize it in Quartis
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Assignment HW 13
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Complete the ALU unit.
Add the remaining internal muxes and internal control
unit that given the operation input, generates the
internal control signals.
Note that for an increment it is easy to simply add one
to the A input. For decrement add FF (-1) to the A
input. (3-1=2 : 0011+1111=0010, 6-1 :
0110+1111=0101)
Once this is complete and synthesizes OK, add input
registers and an output driver to give the unit shown in
the datapath.
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Assignment 14
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This is the final assignment
Integrate the ALU with the register to form a datapath.
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Synthesize it to synthesize a complete datapath. Write a
report that includes the HDL code, the RTL diagram from
synthesis, and the basic synthesis statistics.
Simulate it to load values into the register. You will need
to simulate two logic operations, an add, an increment,
and a decrement. For these show the simulation cycle
where the data is sent to the ALU and the simulation cycle
where the result is returned to the register. Be sure the
show the busses, and the control signals on the simulation
waveform and explain them in the text of the report.
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Start to put the unit together
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The Units
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4-to-1 Mux
ENTITY mux4to1 IS
PORT (G3,G2,G1,G0,S1,S0 : in bit;
R : OUT bit);
END mux4to1;
ARCHITECTURE one OF mux4to1 IS
BEGIN
R <= (G0 AND NOT S1 AND NOT S0) OR
(G1 AND NOT S1 AND S0) OR
(G2 AND S1 AND NOT S0) OR
(G3 AND S1 AND S0);
END one;
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An 4-to-1 mux by 8-bits
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Create an 8 bit wide version
ENTITY mux4to1x8 IS
PORT (G3,G2,G1,G0 : IN bit;
a : IN bit_vector (7 downto 0);
b : IN bit_vector (7 downto 0);
r : OUT bit_vector (7 downto 0));
END mux4to1x8;
ARCHITECTURE one OF mux4to1x8 IS
COMPONENT mux4to1
PORT (G3,G2,G1,G0,S1,S0 : in bit;
R : OUT bit);
END COMPONENT;
FOR all : mux4to1 USE ENTITY work.mux4to1(one);
BEGIN
u0 : mux4to1 PORT MAP (G3,G2,G1,G0,a(0),b(0),r(0));
u1 : mux4to1 PORT MAP (G3,G2,G1,G0,a(1),b(1),r(1));
u2 : mux4to1 PORT MAP (G3,G2,G1,G0,a(2),b(2),r(2));
u3 : mux4to1 PORT MAP (G3,G2,G1,G0,a(3),b(3),r(3));
u4 : mux4to1 PORT MAP (G3,G2,G1,G0,a(4),b(4),r(4));
u5 : mux4to1 PORT MAP (G3,G2,G1,G0,a(5),b(5),r(5));
u6 : mux4to1 PORT MAP (G3,G2,G1,G0,a(6),b(6),r(6));
u7 : mux4to1 PORT MAP (G3,G2,G1,G0,a(7),b(7),r(7));
END one;
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What now?
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Already have a 2 to 1 x 8-bit mux.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mux2to1x8 IS
PORT (linput,rinput : IN std_logic_vector(7 downto 0);
sel : IN std_logic;
dataout : OUT std_logic_vector(7 downto 0));
END mux2to1x8;
ARCHITECTURE one OF mux2to1x8 IS
BEGIN
dataout <= linput WHEN sel='1' ELSE rinput;
END one;
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Create an 8 bit adder
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Simple a ripple carry adder. Start with a full adder
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY full_add IS
PORT (A,B,Cin : IN std_logic;
Sum,Cout : OUT std_logic);
END full_add;
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ARCHITECTURE one OF full_add IS
BEGIN
Sum <= A XOR B XOR Cin;
Cout <= (A AND B) OR (A AND Cin) OR (B AND Cin);
END one;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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An 8-bit adder
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY add8 IS
PORT (A,B : IN std_logic_vector (7 downto 0);
Cin : IN std_logic;
Cout : OUT std_logic;
Sum : OUT std_logic_vector (7 downto 0));
END add8;
ARCHITECTURE one OF add8 IS
COMPONENT full_add IS
PORT (A,B,Cin : IN std_logic;
Sum,Cout : OUT std_logic);
END COMPONENT;
FOR all : full_add USE ENTITY work.full_add(one);
SIGNAL ic : std_logic_vector (6 downto 0);
BEGIN
a0 : full_add PORT MAP (A(0),B(0),Cin,Sum(0),ic(0));
a1 : full_add PORT MAP (A(1),B(1),ic(0),Sum(1),ic(1));
a2 : full_add PORT MAP (A(2),B(2),ic(1),Sum(2),ic(2));
a3 : full_add PORT MAP (A(3),B(3),ic(2),Sum(3),ic(3));
a4 : full_add PORT MAP (A(4),B(4),ic(3),Sum(4),ic(4));
a5 : full_add PORT MAP (A(5),B(5),ic(4),Sum(5),ic(5));
a6 : full_add PORT MAP (A(6),B(6),ic(5),Sum(6),ic(6));
a7 : full_add PORT MAP (A(7),B(7),ic(6),Sum(7),Cout);
END one;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The decoder
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Step 1 – select encoding
4 input bit for operation - oper (3 downto 0)
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0000
0001
0010
0011
0100
0110
1000
1001
1010
1011
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add
add with carry
subtract
subtract with carry
increment
decrement
and
or
xor
not A
Copyright 2012 - Joanne DeGroat, ECE, OSU
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The muxes
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Output mux
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Carry in mux
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Control is oper(0) = 0 – select the 0 side
1 – select the cin side
B input or fixed val for increment/decrement
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Control is oper(3) = 1 – select logic
0 - select adder
Control is oper(2) = 0 – select B input
1 – select fixed val
Fixed value mux
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Control is oper(1) = 0 – select increment side $01
1 – select decrement side (-1) $FF
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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For logic operation generate Gs
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1000 - and
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1001 - or
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Want 0110
1011 - not A
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Want G(3 dt 0) =1110
1010 - xor
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Want G(3 dt 0) = 1000
Want 0011
Use logic equations to generate the Gs.
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Can treat the coding for arithmetic operation as don’t
cares on K maps - example
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Final step
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Create entity for ALU unit
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ENTITY alu IS
PORT (a,b : IN bit_vector (7 downto 0);
cin : IN bit;
oper : IN bit_vector (3 downto 0);
result : OUT bit_vector(7 downto 0));
END alu;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Then create the architecture
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This is the assignment.
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Questions???
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