Lecture 18 VHDL for other counters and controllers

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L18 – VHDL for other
counters and controllers
Other counters
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More examples
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Gray Code counter
Controlled counters
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Up down counter
Ref: text Unit 10, 17, 20
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Gray code counter
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What is Gray Code – it is a binary encoding
that has only one bit transition from 0 to 1 or
1 to 0 in any successive count.
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3 bit sequence – 3 bit Gray code count
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000 – 001 – 011 – 010 – 110 – 111 – 101 – 100 – 000
How to generate?
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Actually quite easy and controlled
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Gray Code generation
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Start with the one bit
For 2 bit, put 1-bit code as lsb
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Precede by a 0 on 1 bit code
Precede by a 1 on reflected 1 bit code
Results in 2-bit count sequence
For n bit Gray Code
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Precede by a 0 on n-1 Gray bit code
Precede by a 1 on reflected n-1 Gray bit code
Results in n-bit count sequence
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The HDL code for a 3 bit counter
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The counter is a SED counter
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What is SED – Single Error Detecting
SED will detect any single error that occurs in the architecture of the
counter. This was for a specific purpose. Can easily be modified to
be non SED.
Only gives an indication (output signal) that error occurred.
The ENTITY
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ENTITY cnt3 IS
PORT (clk : IN bit;
cnt : OUT bit_vector(2 downto 0);
dcnt : OUT bit_vector(2 downto 0);
err : OUT bit);
END cnt3;
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The declarative region
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ARCHITECTURE one OF cnt3 IS
SIGNAL state,next_state : bit_vector(2 downto 0) := "000";
SIGNAL dstate,dnext_state : bit_vector(2 downto 0) := "111";
BEGIN
A binary encoded state machines
Two state machines are being specified
Each has state encoding of 3 bits
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The F/F process
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Note that both state machine Flip Flops are
specified within the same process. This is
acceptable.
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-- Latching logic specification
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
dstate <= dnext_state;
END PROCESS;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Next state processes(2 of them)
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--Next state logic for true logic
PROCESS (state)
BEGIN
CASE state IS
WHEN ("000") =>
next_state <= "001";
WHEN ("001") =>
next_state <= "011";
WHEN ("011") =>
next_state <= "010";
WHEN ("010") =>
next_state <= "110";
WHEN ("110") =>
next_state <= "111";
WHEN ("111") =>
next_state <= "101";
WHEN ("101") =>
next_state <= "100";
WHEN ("100") =>
next_state <= "000";
END CASE;
END PROCESS;
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--Next state logic for dual logic
PROCESS (dstate)
BEGIN
CASE dstate IS
WHEN ("111") =>
dnext_state <= "110";
WHEN ("110") =>
dnext_state <= "100";
WHEN ("100") =>
dnext_state <= "101";
WHEN ("101") =>
dnext_state <= "001";
WHEN ("001") =>
dnext_state <= "000";
WHEN ("000") =>
dnext_state <= "010";
WHEN ("010") =>
dnext_state <= "011";
WHEN ("011") =>
dnext_state <= "111";
END CASE;
END PROCESS;
Copyright 2012 - Joanne DeGroat, ECE, OSU
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The output process
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Again quite simple
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--Assign outputs
cnt <= state;
dcnt <= dstate;
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err <= (state(0) XNOR dstate(0)) OR (state(1) XNOR dstate(1))
OR (state(2) XNOR dstate(2));
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END one;
Note: As binary encoded output, output process can be a simple
concurrent signal assignment. Also, generate the error signal
output which is a direct Boolean function of the state encoding
bits.
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Description of Quartis results
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What would be expected?
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CLASS INPUT
Run through Quartis successfully
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Quartis schematic result
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The schematic
6 F/F (2 3-bit counters)
6 combinational elements
with register
2 combinational elements
with no register ??
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Error signal generation
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Up/Down Counter
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An Up/Down counter is a controlled counter
Specification: Design a 3-bit counter that has
an input c which indicates that the counter
should be counting, an input r that resets the
counter to 0 when asserted, and an input ud
which says to count up when ud=1 and count
down when ud=0.
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The HDL interface
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THE ENTITY
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ENTITY cnt3ud IS
PORT(clk,c,r,ud : IN BIT;
cnt : OUT bit_vector(2 downto 0));
END cnt3ud;
This time there are several control signals in
ENTITY
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The declarative region
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Start the ARCHITECTURE and state element process
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ARCHITECTURE one OF cnt3ud IS
-- will use a binary encoded state
SIGNAL state,next_state : bit_vector(2 downto 0) := "000";
BEGIN
--state elements
PROCESS
BEGIN
WAIT UNTIL clk='1' AND clk'event;
state <= next_state;
END PROCESS;
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Next state
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This is where the input control affects the behavior of the machine.
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--next state process
PROCESS (state,c,r,ud)
BEGIN
CASE state IS
WHEN "000"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "000";
ELSIF (ud='1') THEN next_state <= "001";
ELSE next_state <= "111";
END IF;
WHEN "001"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "001";
ELSIF (ud='1') THEN next_state <= "010";
ELSE next_state <= "000";
END IF;
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Next state continued
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WHEN "010"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "010";
ELSIF (ud='1') THEN next_state <= "011";
ELSE next_state <= "001";
END IF;
WHEN "011"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "011";
ELSIF (ud='1') THEN next_state <= "100";
ELSE next_state <= "010";
END IF;
WHEN "100"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "100";
ELSIF (ud='1') THEN next_state <= "101";
ELSE next_state <= "011";
END IF;
WHEN "101"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "101";
ELSIF (ud='1') THEN next_state <= "110";
ELSE next_state <= "100";
END IF;
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The end of the next state process
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WHEN "110"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "110";
ELSIF (ud='1') THEN next_state <= "111";
ELSE next_state <= "101";
END IF;
WHEN "111"=> IF (r='1') THEN next_state <= "000";
ELSIF (c='0') THEN next_state <= "111";
ELSIF (ud='1') THEN next_state <= "000";
ELSE next_state <= "110";
END IF;
END CASE;
END PROCESS;
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The output process
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Again quite simple
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--output process
cnt <= state;
END one;
Before going off to synthesis the description
needs to be simulated.
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The testbench
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The start
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ENTITY testcnt3ud IS
END testcnt3ud;
ARCHITECTURE one OF testcnt3ud IS
COMPONENT cnt3ud IS
PORT(clk,c,r,ud : IN BIT;
cnt : OUT bit_vector(2 downto 0));
END COMPONENT;
FOR all : cnt3ud USE ENTITY work.cnt3ud(one);
--declare hookup signals
SIGNAL clk,c,r,ud : bit;
SIGNAL cnt : bit_vector (2 downto 0);
BEGIN
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The common setup of clk
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And wire in the component
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--set up clock - 50% duty cycle - 10 ns period
clk <= NOT clk AFTER 5 ns;
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--instantiate component
u1 : cnt3ud PORT MAP (clk,c,r,ud,cnt);
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Now generate the controls
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--generate control signal stimulus
PROCESS
BEGIN
--time 0 -- set up controls
c <= '1'; -- count
r <= '0'; -- don't reset
ud <= '1'; -- count up
WAIT for 100 ns; -- allow the
system to count
--reset the counter
r <= '1';
WAIT for 10 ns;
r <= '0'; -- start counting again
WAIT for 50 ns;
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--start counting down
ud <= '0';
WAIT for 100 ns;
--flip back to counting up
ud <= '1';
WAIT for 50 ns;
--now hold count
c <= '0';
WAIT for 50 ns;
--now resume
c <= '1';
WAIT for 50 ns;
--should be done!
WAIT;
END PROCESS;
Copyright 2012 - Joanne DeGroat, ECE, OSU
21
The waveform
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The first 120 ns – count then reset
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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The waveform
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From 120 to 270 ns – counting down
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The waveform
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After 270 ns – suspend count
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Enter into Quartis
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And synthesize –
this is a somewhat
more complex
design
3 registers
7 I/O pins
5 LUTs
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Time for live demo
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Demo of code in Modelsim
Demo of setup in Quartis
Probably want to take note of steps and
editing shortcuts.
9/2/2012 – ECE 3561 Lect
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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Lecture summary
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HDL for more complex counter
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HDL for controlled counter
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HDL code
Testbench
Testbench needing control signal wave forms
Simulation results
Quartis results
Coming – TYPE std_logic
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Copyright 2012 - Joanne DeGroat, ECE, OSU
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