Measuring Network
Performance of Multi-Core
Multi-Cluster (MCMCA)
Norhazlina Hamid
nh3g11@ecs.soton.ac.uk
Supervisor: R J Walters and G B Wills
PUBLIC SERVICE DEPARTMENT OF MALAYSIA
Outline
 Introduction and Definition
 Motivation
 Related Work
 Research Objectives
 The Architecture
 Methodology
 Conclusion and Progress Work
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Introduction
 The emergence of High Performance
computing (HPC) that includes Cluster
computing has improved the availability
of powerful computers and high speed
network technologies.
 The implementation of multi-core cluster
as a platform of high performance
network will supports high availability
and enables scalability of the networks. 3
Definition
 Multi-Core Multi-Cluster Architecture
(MCMCA) is a collection of multiple multicore cluster, interconnect by a network.
 MCMCA are built from:
 Cluster computing is a collection of
computer, interconnect by a network which
work together to form a single computer
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Definition
 A multi-core cluster is a cluster where some
or all the nodes in the cluster have multicore processors
 Multi-cluster architecture is a multiple
cluster system that is connected via the
cluster interconnection networks
Cluster
computi
ng
Multicore
process
or
Multicluster
MCMCA
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Motivation
 Existing models do not address the
potential performance of the
interconnection networks within large-scale
multi-core clusters .
 A high communication latency of
interconnection network can dramatically
reduce the efficiency of the cluster system.
 Scaling up by adding more processors to
each cluster increase the processing power.6
Related Works
 Furhad et al. (2013) proposed the EnMesh
topology to address the issue of
communication delays that occur with long
distance communication within the remote
nodes of a NoC.
 Mohsen et al. (2013) proposed a new
mapping technique to assign parallel
processes into processing cores of a multicore cluster which based on queuing
network modelling of a limited-size cluster. 7
Objectives
 To propose a new architecture for multicore multi-cluster.
 To investigate the performance of
interconnection networks of multi-core
multi-cluster architecture.
 To demonstrate the feasibility of the
proposed architecture by computer
simulation experiment and measurements.
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The Architecture of MCMCA
Extended Multi-core Cluster System Architecture (EMCSA)
Cluster 0
Inter-Chip
Intra-Chip
Core
Core
Core
Core
Cluster 1
Inter-Chip
Intra-Chip
Core
Core
Core
Intra-Chip
Core
Inter-Chip
Core
Core
Core
Core
Inter-Chip
Intra-Chip
Core
Core
Core
Core
Cache Cache
Cache Cache
Cache Cache
Cache Cache
Cache Cache
Cache Cache
Cache Cache
Cache Cache
Dual-Core Chip
Dual-Core Chip
Dual-Core Chip
Dual-Core Chip
Dual-Core Chip
Dual-Core Chip
Dual-Core Chip
Dual-Core Chip
Memory
Memory
Memory
Memory
Memory
Memory
Memory
Memory
Key:
Intra-Chip
:
Inter-Chip
:
Intra-Cluster Network :
Inter-Cluster Network :
Multi-Cluster Network:
Intra-Cluster Network (ACN)
Intra-Cluster Network (ACN)
Inter-Cluster Network (ECN)
Inter-Cluster Network (ECN)
Multi-cluster Network (MCN)
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Communication Network
 There are five communication networks in
MCMCA
1.
2.
3.
4.
5.
IntrA-chip Communication network (AC)
IntEr-chip Communication network (EC)
IntrA-Cluster Network (ACN)
IntEr-Cluster Network (ECN)
Multi-Cluster Network (MCN)
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IntrA-chip Communication network (AC)
Message passing between two processor cores on
the same chip
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IntEr-chip Communication network (EC)
Message passing across processors on
different chips but within a node
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IntrA-Cluster Network (ACN)
Message passing between processors on
different nodes but within the same cluster
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Communication Network
Message passing between clusters
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Methodology
 Computer simulation experiments using
OMNeT network simulation tool.
 Focus on network latency to measure the
performance.
 Early stage experiments are based on a
single-core multi-cluster architecture.
 The experiments have been performed
using given configuration and parameters
of previous paper to create baseline results.15
Experiment Results
 Results from the experiments have shown
that as the traffic rate increases, the
average communication latency increases
following the assumptions that the
messages are delayed by having to wait for
resources before traversing into a network.
 The results confirm that the simulation
model is a good basis to measure the
communication latency for a large-scale
cluster, and can be extended to multi-core
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multi-cluster architecture.
Methodology
 Network Latency (∑NL) are obtained from:
– Total Network Latency of Message Passing
Within Cluster (L)
– Total Network Latency of Message Passing
Between Clusters (L)
– Probability of outgoing message in a cluster
(P)
– Probability of message in a cluster (1-P)
 Analytical Formula:
∑NL = (L x (1-P)) + (L x P)
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Methodology
 Both Network Latency (L and L) are
obtained from:
– Waiting time at the source node (W)
– Delay while traversing the network(D)
– Time for each packet to reach its
destination node (E)
– Waiting time at transfer switch between
clusters (Wts)
 Analytical Formula:
L = W + D + E
L = W + D + E + 2Wts
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Conclusion
 Presenting a new architecture for
measuring the performance of
interconnection networks in MCMCA.
 Progress work:
1. Developing a MCMCA simulation model.
2. Conduct a simulation experiments with
different network technology and
bandwidth.
3. Developing analytical equation for the
architecture.
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Published Paper
1. Hamid, Norhazlina, Walters, Robert John and Wills, Gary
Brian (2014) Performance evaluation of multi-core multi-cluster
architecture. In, Emerging Software as a Service and
Analytics, Barcelona, ES,03 - 05 Apr 2014. Scitepress9pp, 4654.
2. Hamid, Norhazlina, Walters, Robert John and Wills, Gary Brian, "
An Architecture for Measuring Network Performance in MultiCore Multi-Cluster Architecture (MCMCA). In, Euro-Asia
Conference on Computational Intelligence and Communication
Networks, Antalya, Turkey, 21-23 Apr 2014."
3. Hamid, Norhazlina, Walters, Robert John and Wills, Gary Brian, "
An Architecture for Measuring Network Performance in MultiCore Multi-Cluster Architecture (MCMCA)," International Journal
of Computer Theory and Engineering vol. 7, no. 1, pp. 57-61,
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February 2015.
Q&A
Thank you.
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