Floorplanning and Signal Assignment
for Silicon Interposer-based 3D ICs
W. H. Liu, M. S. Chang and T. C. Wang
Department of Computer Science,
NTHU, Taiwan
DAC 2014
Outline
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Introduction
Preliminaries
Enumeration-based Floorplanning Algorithm
Network-flow-based Signal Assignment
Experimental Results
Conclusions
Introduction
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Interposer-based 3D ICs (2.5D ICs) have been
seen as an alternative approach to true 3D stacked
ICs.
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2.5D ICs use a silicon interposer as an interface
between a package and dies, and mount each die
on the interposer.
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2.5D ICs are easier to fabricate than true 3D ICs,
making 2.5D ICs become more popular.
Introduction
Introduction
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This paper assumes that the placement and routing
in each die are already finished.
The locations of the I/O buffers in each die are
determined.
The work focuses on optimizing the multi-die
floorplanning and signal assignment in a 2.5D IC to
minimize the total wirelength.
Preliminaries
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Wirelength Evaluation
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The interconnects to deliver signals in 2.5D ICs
are classified into three types of nets:
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Intra-die nets
Internal nets
External nets
The total wirelength (TWL) is measured by:
Problem Formulation
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Multi-die Floorplanning Problem:
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Given:
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D: a set of dies in a 2.5D IC
S: a set of signals
B: a set of I/O buffers in each die
E: a set of escaping points at the boundaries of the
package on the PCB
A fixed outline silicon interposer
Output:
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Find a floorplan F of all dies in D on the interposer
Die-to-die and die-to-boundary spacing constraints are
imposed and need to be satisfied
Problem Formulation
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Signal Assignment Problem
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Given
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F: a floorplan
S: a set of signals
B: a set of I/O buffers in each die
M: a set of micro-bumps in each die
E: a set of escaping points at the boundaries of the package
on the PCB
T: a set of TSVs in the interposer
Output
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Assign the signal of each I/O buffer in B to a micro-bump in
M
Assign the signal of each escaping point in E to a TSV in T
such that no micro-bump or TSV is assigned more than one
signal
Problem Formulation
Multi-die floorplanning result
Signal assignment result
Enumeration-based
Floorplanning Algorithm
Violate the
fixed outline
constraint or
the spacing
constraints
Estimate TWL by adding up
the HPWL of all terminals for
every signal.
Enumeration-based
Floorplanning Algorithm
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Illegal Branch Cutting
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Each sequence pair with different die orientations provides
at most 4n different floorplans.
If a SP does not provide any legal floorplans, we can avoid
exploring the floorplans of this SP.
Flow : rotate each die to make its height not greater than its
width.
Fthin : rotate each die to make its width not greater than its
height.
If Flow is taller than the interposer or Fthin is wider than the
interposer, SP has no legal floorplan.
Enumeration-based
Floorplanning Algorithm
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Inferior Branch Cutting
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If we can predict that all floorplans of a SP are worse than
the current Fbest, we can avoid exploring the floorplans of
the SP.
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Let Lmin denote a lower bound on WL with respect to a SP.
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If Lmin is longer than the WL of Fbest, we can claim that all
floorplans of SP are worse than Fbest. The exploration of
the floorplans of SP can be skipped.
Enumeration-based
Floorplanning Algorithm
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Inferior Branch Cutting
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Let Lmin consist of LXmin and LYmin.
Estimate LYmin by adding up the minimum
vertical WL of each signal in Flow.
Enumeration-based
Floorplanning Algorithm
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Die Orientation Pre-determination
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Generate a reference floorplan Fref before EFA.
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EFA only explores the floorplans whose die orientations
are the same as Fref.
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Two-stage greedy packing algorithm
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Choose a best pair of dies and packs them together to form
the initial Fref.
Iteratively attach one of unpacked dies to until all dies are
packed into Fref.
Enumeration-based
Floorplanning Algorithm
Puts Fpair to the center
of interposer, calaulate
the total HPWL of all
signals in Fpair
If Fpair is illegal, a very
large penalty is added
to the cost of Fpair
Enumeration-based
Floorplanning Algorithm
Network-flow-based Signal
Assignment
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Divide the SAP into several sub problems.
First solve the sub-SAP for micro-bumps die-by-die.
Solve the sub-SAP for TSVs.
Solve the sub-SAP for each die in a decreasing
order based on the number of I/O buffers in each
die.
Network-flow-based Signal
Assignment
Network-flow-based Signal
Assignment
Network-flow-based Signal
Assignment
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Window Matching Method to Accelerate
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Use a window matching method to identify the assignment
candidates for each I/O buffer.
For each I/O buffer bi,x, create a window wi,x whose center
is bi,x, and its width and height are 2xmpitch, where mpitch
denotes the pitch between micro-bumps.
If M(wi,x)-B(wi,x)<, iteratively extend each boundary of wi,x
by mpitch until M(wi,x)-B(wi,x)≥.
Only build the edges from each I/O buffer bi,x to the microbumps in wi,x.
Experimental Results
Experimental Results
Experimental Results
Experimental Results
Conclusions
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This paper addresses a multi-die floorplanning
problem and a signal assignment problem to
shorten the interconnects in 2.5D ICs.
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An enumeration-based floorplanning algorithm is
presented with three acceleration techniques.