VLSI
Prof. Vojin G. Oklobdzija
References (used for creation of the presentation material):
[1] Mead, Conway, “Introduction to VLSI Systems”, Addison
Wesley Publishing.
[2] Glasser, Dobberpuhl, “The Design and Analysis of VLSI
Circuits”, Addison Wesley Publishing.
[3] Weste, Eshraghian, “Principles of CMOS VLSI Design”,
Addison Wesley Publishing.
[4] Shoji, “CMOS Digital Circuits Technology”, Prentice Hall.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
1
Historical Overview
• nMOS era: 1970-85
• Pass-transistor design
• Domino CMOS, 1982
– NORA
– DCVSL
• CPL, DPL
– DCVS-PG
– SRPL
– LEAP
• SOI-CMOS
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
2
n-MOS Design Era
LSI started with nMOS:
• pass-transistor design experience:
- Flourished at the beginning of the nMOS era
(popularized by Mead-Conway book)
- Allows high density layout and compact design style
- Fast: outperforming gate based design
- Low in power
• Drawbacks:
– Not compatible with existing design tools
– Exhibiting testability and reliability problems
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
3
Pass-Transistor Design
Another way of looking at Karnaugh Map: AND function
A
A
B
F
0
1
0
0
1
1
1
0
F
B
B
A
Prof. V.G. Oklobdzija
B
Advanced Digital Integrated Circuits
B
4
Pass-Transistor Design
A
X
F
Y
A
Two-variable function
Prof. V.G. Oklobdzija
X
0
0
1
1
0
0
1
1
B
B
B
B
B
B
B
B
Y
0
1
0
1
B
B
B
B
0
1
0
1
B
B
F
0
A
A
1
AB
AB
AB
AB
AB
AB
A+B
A B
B
B
A B
A B
B
B
Advanced Digital Integrated Circuits
5
Pass-Transistor Design
“Threshold Voltage Drop” problem:
A=Vdd
+ V
th
-
B=Vdd
Fmax = Vdd-Vth
B
Vdd
Vdd
Vdd
+ V V
+
th
th
--
Fmax = Vdd-Vth
Cout
Cout
A
(a)
Prof. V.G. Oklobdzija
(b)
Advanced Digital Integrated Circuits
6
Pass-Transistor Design
Solving the “Threshold Voltage Drop” problem in CMOS:
+Vdd
A=Vdd
+ V
th
Vdd
+ V
th
Fmax= Vdd
In=Vdd
ON
Vdd
+
Cout
Cin
Vdd A=0V
(a)
Prof. V.G. Oklobdzija
(b)
Advanced Digital Integrated Circuits
7
Pass-Transistor Design
A
A
B
B
P0
P1
F(A,B)
P2
P3
Function Generator
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
8
Pass-Transistor Design
Full 1-bit Adder
A
S
A
A
S
CO
A
A
CO
B
Prof. V.G. Oklobdzija
B
C
C
Advanced Digital Integrated Circuits
9
Pass-Transistor Design
Compact ALU
Example
(IBM PC/RT)
Circ. 1984
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
10
Control Lines
Output
Control
A - inputs
Odd
Operation
B - inputs
Even
Odd
A
Even
K1
K2
Qn
A
B
B
Odd
Even
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
1
0
0
1
Arithmetic
A+B
Add
A+B+1
A-B
Subtract
0
0
1
0
1
1
0
1
0
0
1
0
1
B-A
Subtract
0
0
1
1
0
0
1
0
1
1
0
0
1
B+1
Increment
0
0
1
1
1
0
0
0
1
1
0
0
1
+1
2s compl
0
0
1
1
1
0
0
1
0
0
1
0
1
A+1
Increment
0
0
1
0
1
1
0
1
1
0
0
0
1
+1
2s compl
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
B
1
1
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
0
1
1
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
1
1
Logical
0
A
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
11
Pass-Transistor Design
Function Generator
VH
Compact ALU
Example
(IBM PC/RT)
f
A
B
A
B
K2
CO
K2
VH
CO
CI
K2
A
K1
A
B
B
Carry Generator
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
12
Using Pass-Transistor Design to Speed-up
Addition
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
13
Review of CMOS
Prof. Vojin G. Oklobdzija
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
14
CMOS Basics
Vdd
Karnaugh Map
of Function F
( A + B)
A
F
0
1
0
1
1
1
1
0
F
B
(A
A
B)
B
C
Function F and its Dual
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
15
CMOS Basics
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
16
CMOS Basics
covering ones :
D( A + B C )
B
A
D
C
D
1
0
0
1
1
0
0
1
B
F
0
0
0
0
1
0
0
0
A
A
covering zeroes :
D + A (B +C)
B
Prof. V.G. Oklobdzija
C
D
D
Advanced Digital Integrated Circuits
17
CMOS Basics
A complex path example:
VDD
E
B
D
A
C
Output
A
B
C
D
E
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
18
CMOS Basics
Primitive gates:
Prof. V.G. Oklobdzija
More complex blocks
are realizable in CMOS
Advanced Digital Integrated Circuits
19
CMOS Deficiencies:
Muli-Input NOR function
in CMOS is slow
Various remedies:
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
20
CMOS Deficiencies and Remedies
Faster, one-level
realizations of XOR
function
XOR
A
A
B
AB
B
+
AB
AB
+
AB
B
(b)
(a)
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
21
CMOS Deficiencies and Remedies
XNOR
Faster, one-level
realizations of XOR
function
A
AB
+
AB
AB
+
AB
B
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
22
CMOS Basic
Inverter Transfer function:
Logic voltage levels are VOH and VOL
and VIL and VIH
The inverter transfer function lie
within the shaded region
VDD
VOH
VIH
Vout
VIL
VOL
0
VOL
VIL
VIH
VOH
VDD
Vin
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
23
CMOS Basic: Inverter Characteristic
p “ON”
n “OFF’’
BOTH p & n “ON”
A
p ”OFF”
n ”ON”
B
VDD
0.5VDD
C
D
E
0
0
Prof. V.G. Oklobdzija
Vtn
0.5VDD
VDD + Vtp
Advanced Digital Integrated Circuits
VDD
24
CMOS Basic: Inverter Characteristic
VDD
VDD
T2
V0(t)
Vin(t)
T1
t
CL
+ VDD
0
t
+ VDD
0.9 VDD
0.1 VDD
t
td
tf
Prof. V.G. Oklobdzija
tr
Advanced Digital Integrated Circuits
25
CMOS Basic: Inverter Characteristic
Transistors during the transition
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
26
CMOS Basic: Inverter Switching
VDD
p-DEVICE
VDD
p-DEVICE
t=0
Ic
Ic
CL
R
c
VO
n-DEVICE
CL
VO
n-DEVICE
SATURATION :
VO  VDD  Vin
VDD
p-DEVICE
LINEAR :
0  VO  VDD  Vin
VDD
p-DEVICE
R
c
Ic
Ic
t=0
CL
n-DEVICE
VO
SATURATION
Prof. V.G. Oklobdzija
CL
n-DEVICE
VO
LINEAR
Advanced Digital Integrated Circuits
27
CMOS Basic: Power
tp
VDD
• During the static state there is
no current
V
0
tf
• Current is only present during
transistion:
tr
t
VDD
V
-
-
Short circuit current (crow-bar
current)
Charging and discharging of the
output capacitor
Leakage Current
0
VDD
I
0
Prof. V.G. Oklobdzija
t
Advanced Digital Integrated Circuits
t
28
CMOS Basic: Power
PCMOS=kCLV2DDfo
This is an E=mc2 of low-power design
There are three ways to control power:
- Reducing Power-Supply Voltage (most effective !!)
- Reducing the switching activity k (various ways)
- Reducing CL (technology scaling etc.)
- Reducing the required frequency of operation (?)
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
29
CMOS Basic: Delay
• Which one of the three designs is the fastest ?
• How can we find this out without simulation ?
a7
Case 1
CL
a0
(a)
a7
Case 3
a7
a6
a5
a4
a3
a2
a1
Case 2
CL
a0
(c)
a4
CL
a3
a0
(b)
Prof. V.G. Oklobdzija
Learn about Logical Effort !
Advanced Digital Integrated Circuits
30
CMOS Basic: Delay
Charge:
Ic
Cin1
Cin2
Discharge
Id
Discharge
Id
Prof. V.G. Oklobdzija
Cout
Advanced Digital Integrated Circuits
31
CMOS Basic: Delay
RNOR
Ic
Id
RND7
Id
Cin1
Cin2
RND2
Cout
Delay can be approximated with:
RND7Cin1+RNORCin2+RND2Cout
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
32
CMOS Basic: Delay
Delay of a signal path in CMOS logic is dependent
on:
• Fan-in of a gate
– Represented as a resistance of the pull-up/down
transistor path of the gate
• Fan-out of a gate
– Represented as a capacitive load at the output
• Number of CMOS blocks in the path.
• Wire delay connecting various blocks.
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
33
CMOS Basic: Delay
Delay of a signal path in CMOS logic can be
reduced by:
• Making the transistors larger in order to minimize
resistance of a pull-up/down path in the gate
• Making the transistors smaller in order to
minimize the capacitive load of each gate
• Reducing the number of CMOS blocks in the path.
• Bringing the blocks closer and/or choosing the
less wire intensive topology.
– Note that these requirements are often contradictory
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
34
CMOS Basic: Delay
• How to estimate delay and critical timing in
CMOS circuits ?
• How to determine the proper transistor sizing in
order to make a compromise with contradicting
requirements ?
• How to choose the right circuit topology ?
The Answer:
“Logical Effort”
Prof. V.G. Oklobdzija
Advanced Digital Integrated Circuits
35