ECE 465
Lecture Notes # 1
Introduction to Digital Design
Shantanu Dutt
ECE Dept.
UIC
Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
—the analog BW is proportional to n, the
the # of distinct values or levels, while the corresponding digital BW
is proportional to log n (or more exactly to Vdd(log n))
Copyright: Shantanu Dutt
i.e., 2’s complement number system, floating-point number system, etc.
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 Pure if-then-else type constructs can be implemented using
combinational circuits
 Loops generally need to be impl. using sequential circuits,
since the circuit/system needs to “remember” where it is in the loop
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Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
Copyright: Shantanu Dutt
There are two switches S1 and S2 to control the a light bulb (e.g., one
switch near each door of a room w/ 2 doors). Design a logic circuit so that
the bulb can be controlled (essentially, toggled) by either switch (i.e., by
flicking/pushing either switch).
S1
S2
Z
S1
Diff. initial
conditions
S2
Z
np/0 np/0 0
np/0 np/0 1
np/0 p/1
np/0 p/1
1
0
p/1
np/0 1
p/1
np/0 0
p/1
p/1
p/1
p/1
0
1
1-switch flick
transition arrows
(verifying consistency Legend: np: not pushed (or, say, “up” posn)
of corresponding
p: pushed (or, say, “down” posn)
o/p transitions)
Design Steps (for small-size designs w/ up to around 6 vars; we will later learn
about hierarchical or divide-and-conquer strategies for larger designs)
1a. If TT can be obtained directly (due to the nature of the problem statement), then
encode inputs and outputs, get the TT, and go straight to the minimization step (Step
4).
Otherwise go to Step 1b.
Copyright: Shantanu Dutt
Alternate Statement
Design Steps (for small-size designs w/ up to around 6 vars; we will later learn
about hierarchical or divide-and-conquer strategies for larger designs)
1b.
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FPGAs—will do later)
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Drain
Source
Drain
Source
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nMOS Transistor – Logic ‘1’
Transfer
VT,MP is the threshold voltage of
the nMOS transistor
Ack: From http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt
Copyright: Shantanu Dutt
nMOS Transistor – Logic
‘0’ Transfer
Ack: From http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt
Copyright: Shantanu Dutt
GATES IN SERIES
Vdd
weak 1
Vdd -Vt
Vdd -2Vt
very weak 1
Vdd -3Vt
Vdd
Vdd -4Vt
Vdd
The output can thus be a very weak 1
Ack: From http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt
Copyright: Shantanu Dutt
CMOS TRANSMISSION & LOGIC GATES
 Thus an nMOS transistor passes a strong 0 and a weak 1.
 A similar analysis (for pMOS, gate to source voltage has to be < the (negative) threhold
voltage VT for transistor to conduct) shows that a pMOS transistor passes a strong 1 and a
weak 0.
 This is the basis of CMOS logic gates, where pMOS transistors are used in the “top” n/w
connected to Vdd to conduct a strong or good 1, and nMOS transistors are used in the
“bottom” or complementary n/w to conduct a strong 0.
 Also, can Combine the two to make a CMOS pass gate, called a transmission gate, which will
pass a strong 0 and a strong 1.
Ack: Partly from http://www.cse.fau.edu/~ankur/courses/IntroVLSIDesign/Pass%20Transistor%20Logic.ppt
Copyright: Shantanu Dutt
Problem w/ Large Switching Networks
• Even though pMOS conducts a good 1, a long series of pMOS transistors for a manyinput gate can deteriorate the signal due to accumulation of small IR drops across the
trannsistors
•Example: Consider an 8-variable NOR function f = (x7+x6+x5+x4+x3+x2+x1+x0)’.
Its implementation using a single n/w is given below; we assume that a pMOS
transistor has a voltage drop of 0.2 V when conducting a ‘1’—which can be considered
conducting a good ‘1’ as by itself this drop is small. Note that f = x7’x6’ ….. x1’x0’
Vdd=3v
x7
x6
x5
x4
x3
x2
x1
x0
0.2 V
0.2 V
0.2 V
0.2 V
0.2 V
0.2 V
0.2 V
0.2 V
Corresponding compl. n/w (f’=x7+x6+….+x1+x0)
GND
f
Vop=1.4V when f=1; not
a reliable logic 1 voltage
(probably in the
grey/forbidden region)
Copyright: Shantanu Dutt
•
•
•
•
Problem with Large Switching Networks (contd)
The solution is using a number of smaller switching n/ws, so that the deterioration of
the signal (‘1’ or ‘0’ logic value) is small.
Further, each small n/w replenishes the logic value at its o/p from Vdd or GND in spite
of the (small) deterioration of the signal at its inputs (assuming these come from other
n/ws). Thus any deterioration from previous n/ws do not propagate to subsequent n/ws
in the circuit, and such deterioration is in fact “corrected” in n/ws fed by slightly
deteriorated signals coming from other n/ws
Thus we need to break down a large function (function w/ many variables—generally >
6) into smaller ones that can each be implemented using smaller n/ws. This happens to
a large extent when a function is represented as an SOP or POS expression (it is
lready broken down into ANDs and ORs) but not always (e.g., an AND or OR term may
have a large # of vars).
E.g., the 8-i/p NOR function f can be decomposed as (and then impl as below):
–
Vdd=3V
f = [(x7+x6+x5+x4) + (x3+x2+x1+x0)]’ = [(x7’x6’x5’x4’)’ + (x3’x2’x1’x0’)’]’ =
NOR(NAND(x7’,x6’,x5’,x4’), NAND(x3’,x2’,x1’,x0’)). Alternatively, f = (x7+..+ x4)’ (x3+..+x0)’ =
NOT(NAND(NOR(x7,..,x4), NOR(x3,..x0)))
Vdd=3V
x7’
x3’ Note: (1) Vth drops accummulate across a series of gates.
But (2) IR drops are rectified across a series of gates.
x6’
x2’
x5’
x1’
x7’
x6’
x5’
x4’
g
h
g
f
Vdd
x4’
x0’
0.2 V
0.2 V
GND
Compl
n/w for g
g (=2.8V for ‘1’)
GND
0.2 V
Compl
n/w for h
0.2 V
f
x3’
x2’
x1’
x0’
h
(=2.6V for ‘1’)
h
(=2.8V for ‘1’)
GND
Compl
n/w for NOR
Copyright: Shantanu Dutt
Problem with Large Switching Networks (contd)
• These small switching networks are called gates
• Thus need to use small to medium-size (<= 4 inputs) gates to
implement large logic functions
0
strong 1
Vdd
strong 1
Vdd
strong 0
0
Vdd
strong 1
Vdd
0
0
A cascade or series of NAND/NOR gates will produce strong 1’s as well as strong 0’s
Copyright: Shantanu Dutt
Circuit Delay
•
•
•
•
•
•
Assume R is the on-resistance of a single nMOS or pMOS transistor.
Then the worst-case “top” network resistance Rtop of a gate gi is the k*R, where k = max. # of
transistors in series in tye top n/w of gi. Similarly, for the resistance Rbot of the “bottom” or
complementary n/w of gi.
If CL is the capacitive load seen by a gate gi (generally = the sum of gate capacitances C of the
transistors of the gate(s) that gi drives), then the delay in gi driving its output from 0  1 is Rtop* CL
and the delay in gi driving its output from 1  0 is Rbot* CL . In general, we define gate res. Rg =
max(Rtop , Rbot), and the delay of its output signal as Rg* CL
Example: For the 2 i/p NAND gate in Fig. 1, Rtop = R (note that in the worst-case only 1 pMOS
transistor is on, so the res. then is R, and *not* R/2), Rbot = 2R. Thus Rg = 2R, and the gate’s output
delay = Rg*CL = 2R*CL . If the gate is driving a 2-input NAND/NOR/AND/OR gate, then = CL= 2C.
The delay of a path = S (output delays of gates on the path). The delay of the path shown in Fig. 2 =
Rg(g1)*CL(g2) + Rg(g2)*CL(g3) + Rg(g3)*CL(g4) + Rg(g4)*CL(op), where CL(op) is the load at the
output of the path. Thus the path delay = 2R*2C + 2R*2C + 2R*2C + 2R* CL(op) = 12RC + 2R*
CL(op). Note that in this delay formulation, we have ignored the “intrinsic” delay d(gi) of a gate gi to
switch from off to on, though these delays can be added to the above formulation, for each gate on
the path. The formulation w/o the d(gi)’s is called the RC delay.
The delay of a circuit is the delay in the longest (max-delay) path of the circuit from primary inputs to
an output
Rg(g1)*CL(g2)
+ Rg(g2)*CL(g3)
+ Rg(g3)*CL(g4)
+ Rg(g4)*CL(op)
g1
g2
g3
g4
A circuit path (g1g2g3g4output)
Fig. 1: CMOS realization of a 2-i/p NAND gate
Fig. 2: A path of a circuit and its delay
Copyright: Shantanu Dutt