Yu-Jie, Liang
Department of Electronics Engineering
National Chiao Tung University s980650@gmail.com
Yu-Jie, Liang 2013

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Yu-Jie, Liang NCTU IEE5011 Memory Systems 2013 2

Fig.1 The trend of recent scaling.
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Program disturb, read disturb, endurance degradation.
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Interference due to the noise; cross-talk issue.
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Dielectric reliability does not scale; breakdown problem and leakage paths.
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Not enough of electrons.
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Die Stacking of 2D-NAND?
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Use 3D IC technology? (TSV?)
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Monolithic 3D IC technology
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Integrally molded concept (TFT-SONOS)
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BE-SONOS
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Bit cost scalable (BiCS)
 Pipe-shaped Bit cost scalable (P-BiCS)
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Vertical stack array transistor (VSAT)
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Terabit cell array transistor (TCAT)
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Vertical Gate (VG)
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Single Crystalline Stacked Array (STAR)
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P-BiCS VSAT TCAT
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Yu-Jie, Liang
VG
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Fig.2 Bit Cost scalability of three dimensional flash memory.
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Fig.3. Architecture of BiCS and Schematic of NAND memory
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Small P/E window, read disturb, low data retention capability.
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Variations in the voltage on the source line.
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Lower select gate in heavily doped is not easily controlled.
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Fig.4. Schematics of (a) BiCS (b) P-BiCS
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Read disturb of P-BiCS is sufficient for MLC operation.
Yu-Jie, Liang NCTU IEE5011 Memory Systems 2013 9

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For good erase speed, wider Vth margin, and better retention
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But difficult to etch metal/oxide multilayer simultaneously.
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Extra area to apply negative bias on WL.
Fig.5. Architecture of TCAT
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 BiCS suffers from WL interconnect, program disturbance, and channel resistance problem.
 The channel current of P-BiCS and TCAT is conducted through a hole drilled through the layers and an additional WL-cut process must be applied to isolate the WL’s in the X direction. They have limited in X pitch scalability due to the corresponding lithography overlay issue involved.
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The cell size of all vertical channel architectures is 6F 2 . It is not suitable for the traditional planar NAND cell size. (minimum F= 40nm~50nm)
 Low read current: As increase in the length of the NAND string, the read current degrades.
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(A) Using junction-free buried channel device [7]:
Fig.6. Architectures of VG charge trapping NAND flash.
Fig. 8 Dumb mode (without any P/E verify) P/E distributions of 3D VG NAND devices..
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Problems:
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Wider distribution caused by grain boundary effect.
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To isolate the SSL gate in X direction. The X pitch scalability will be limited
Fig. 7 Read current with various channel doping.
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(B) Using PN diode decoding structure [8]:
Fig.10. Poly silicon PN diode I/V characteristics
Fig.9. Architectures of the PN diode decoded VG NAND architecture.
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A good PN diode with very low leakage is very important.
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(C) In-layer plural normally-on SSL decoder[6]:
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The first proposed VG NAND uses plural
SSL gates
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BL in multi-layers can be shared together.
Fig.11. Schematic diagram of in-layer normally-on SSL decoder for VG NAND
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Problems:
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SSL devices must be kept in a complex normally-on status. This introduces a linearly increased layer cost.
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As the number of stacked layer increases, the number of SSL gate is increased accordingly.
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Normally-on SSL uses heavy N+ implant in the channel, thus requires careful thermal budget control.
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(D) Island-gate SSL decoding method [9]:
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Each channel BL has its own island-gate
SSL for the selection/decoding.
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As the number of stacked layer increases , the memory layer does not increase the array overhead size but simply change the unit and page number.
Fig.12. Schematic diagram of 3DVG NAND using island-gate SSL decoding method
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Problems:
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The island-gate SSL decoding suffers BL pitch scaling limitation due to the overlay concern between SSL devices.
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(E) Self-aligned IDG SSL decoding method [10]:
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The top portion of the SSL poly gate is removed by an additional mask after WL patterning.
Fig.13. Schematic structure of the IDG decoded VG NAND Flash.
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Need careful optimization of turn-on voltage (+V
SSL
) and inhibit bias (-V inhibit
) in order to cover the often broad IDG (TFT) SSL Vt distribution.
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In (B), (D), (E), the area is largely fixed when stacking more layers. These fundamentally solve the issues in (C) and become more cost effective when stacking more layers.
 In (B), (C), page operation is carried out in one memory layer each time. In
(D), (E), page operation is carried out within all memory selected by one island-gate SSL in one unit, while many parallel units are programmed/read simultaneously.
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Yu-Jie, Liang
Fig.14. (a) Unit structure of 3D NAND Flash memory based on STAR, i.e., “building.”
(b) Equivalent circuit of the building and operation voltage scheme table.
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(1) Single-crystal channel: better performance without grain boundaries.
 (2) Gate-all-around structure (GAA): good current drivability and small subthreshold swing.
 (3) Small intra-layer interference:
 (4) No inter-layer interference:
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(5) Small channel to channel coupling:
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 (A) Extended Sidewall Control Gate (ESCG):
Fig.15. (a) Bird’s-eye view and (b) cross-sectional view of 3D vertical
FG-type cell using ESCG.
Fig.16. Cross-sectional views of the coupling capacitance of the FG.
Yu-Jie, Liang
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Better CG coupling ratio.
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High-speed read/program operation, less interference effect and good reliability.
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 (B) Separated Sidewall Control Gate (SSCG):
Fig. 17. Three-dimensional vertical FG NAND with SSCG. (a) Bird’s eye view and (b) cross-sectional view in WL direction and (c) equivalent circuit of cell arrays.
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Cell size
Current flow direction
P-BiCS
6F 2
U-turn
Gate stack type
TCAT
6F 2
3D-FG
~6F 2
Vertical Multi-U-turn
Device structure
GAA
~4xnm Possible minimum F
Impact of number of layers of memory
Low read current
GAA
~50nm
Low read current
GAA
>>60nm
Low read current
(can be improved)
VG
4F 2
Channel stack type
Horizontal
Double gate
~2xnm
No impact
STAR
6F 2
Horizontal
GAA
~30nm
No impact
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 [1] Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; Katsumata, R.; Kito, M.; Fukuzumi, Y.; Sato, M.; Nagata, Y.; Matsuoka,
Y.; Iwata, Y.; Aochi, H.; Nitayama, A., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density
Flash Memory," VLSI Technology, 2007 IEEE Symposium on , vol., no., pp.14,15, 12-14 June 2007
 [2] Nitayama, A.; Aochi, H., "Bit Cost Scalable (BiCS) technology for future ultra-high density storage memories," VLSI
Technology (VLSIT), 2013 Symposium on , vol., no., pp.T60,T61, 11-13 June 2013
 [3] Katsumata, R.; Kito, M.; Fukuzumi, Y.; Kido, M.; Tanaka, H.; Komori, Y.; Ishiduki, M.; Matsunami, J.; Fujiwara, T.;
Nagata, Y.; Li Zhang; Iwata, Y.; Kirisawa, R.; Aochi, H.; Nitayama, A., "Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra-high density storage devices," VLSI Technology, 2009 Symposium on , vol., no., pp.136,137, 16-18 June 2009
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Byoung-Keun Son; Dong Woo Kim; Kihyun; Jae-Joo Shim; Jin Soo Lim; Kyoung-Hoon Kim; Su Youn Yi; Ju-Young Lim;
Dewill Chung; Hui-Chang Moon; Sungmin Hwang; Jong-Wook Lee; Yong-Hoon Son; Chung, U-in; Lee, Won-Seong,
"Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," VLSI
Technology, 2009 Symposium on , vol., no., pp.192,193, 16-18 June 2009
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[5] Hang-Ting Lue; Shih-Hung Chen; Yen-Hao Shih; Kuang-Yeu Hsieh; Chih-Yuan Lu, "Overview of 3D NAND Flash and progress of vertical gate (VG) architecture," Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th
International Conference on , vol., no., pp.1,4, Oct. 29 2012-Nov. 1 2012
 [6] Wonjoo Kim; Sangmoo Choi; Junghun Sung; TaeHee Lee; Chulmin Park; Hyoungsoo Ko; Juhwan Jung; Inkyong Yoo;
Yoondong Park, "Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage," VLSI
Technology, 2009 Symposium on , vol., no., pp.188,189, 16-18 June 2009
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[7] Hang-Ting Lue; Tzu-Hsuan Hsu; Yi-Hsuan Hsiao; Hong, S.P.; Wu, M.T.; Hsu, F.H.; Lien, N. Z.; Szu-Yu Wang; Jung-Yu
Hsieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Kuang-Yeu Hsieh; Chih-Yuan Lu, "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device," VLSI Technology (VLSIT),
2010 Symposium on , vol., no., pp.131,132, 15-17 June 2010
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[8] Chun-Hsiung Hung; Hang-Ting Lue; Kuo-Pin Chang; Chih-Ping Chen; Yi-Hsuan Hsiao; Shih-Hung Chen; Yen-Hao Shih; Kuang-
Yeu Hsieh; Yang, M.; Lee, J.; Szu-Yu Wang; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu, "A highly scalable vertical gate (VG) 3D
NAND Flash with robust program disturb immunity using a novel PN diode decoding structure," VLSI Technology (VLSIT), 2011
Symposium on , vol., no., pp.68,69, 14-16 June 2011
 [9] Kuo-Pin Chang; Hang-Ting Lue; Chih-Ping Chen; Chieh-Fang Chen; Yan-Ru Chen; Yi-Hsuan Hsiao; Chih-Chang Hsieh; Yen-Hao Shih;
Tahone Yang; Kuang-Chao Chen; Chun-Hsiung Hung; Chih-Yuan Lu, "Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using
Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics," Memory Workshop (IMW), 2012 4th IEEE
International , vol., no., pp.1,4, 20-23 May 2012
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[10] Chih-Ping Chen; Hang-Ting Lue; Kuo-Pin Chang; Yi-Hsuan Hsiao; Chih-Chang Hsieh; Shih-Hung Chen; Yen-Hao Shih; Kuang-Yeu
Hsieh; Tahone Yang; Kuang-Chao Chen; Chih-Yuan Lu, "A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel selfaligned independently controlled double gate (IDG) string select transistor (SSL)," VLSI Technology (VLSIT), 2012 Symposium on , vol., no., pp.91,92, 12-14 June 2012
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Jong-Ho; Hyungcheol Shin; Park, Byung-Gook, "Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked
ARray," Electron Devices, IEEE Transactions on , vol.59, no.1, pp.35,45, Jan. 2012
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YoungKyun Jung; SungYoon Cho; ChangHee Shin; HyunSeung Yoo; SangMoo Choi; Kwon Hong; Aritome, S.; SungKi Park; Sungjoo Hong,
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Devices Meeting (IEDM), 2010 IEEE International , vol., no., pp.29.7.1,29.7.4, 6-8 Dec. 2010
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[13] Moon-Sik Seo; Sung-Kye Park; Endoh, T., "3-D Vertical FG nand Flash Memory With a Novel Electrical S/D Technique Using the
Extended Sidewall Control Gate," Electron Devices, IEEE Transactions on , vol.58, no.9, pp.2966,2973, Sept. 2011
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[14] Moon-Sik Seo; Bong-Hoon Lee; Sung-Kye Park; Endoh, T., "A Novel 3-D Vertical FG NAND Flash Memory Cell Arrays Using the
Separated Sidewall Control Gate (S-SCG) for Highly Reliable MLC Operation," Memory Workshop (IMW), 2011 3rd IEEE International , vol., no., pp.1,4, 22-25 May 2011
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Lu; Jung-Yu Hsieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Kuang-Yeu Hsieh; Rich Liu; Chih-Yuan Lu, "A novel buried-channel
FinFET BE-SONOS NAND Flash with improved memory window and cycling endurance," VLSI Technology, 2009 Symposium on , vol., no., pp.224,225, 16-18 June 2009
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