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TAIST ICTES Program
VLSI Design Methodology
Hiroaki Kunieda
Tokyo Institute of Technology
1.VLSI Overview
1. Fabrication process such as CMOS process must be decided in prior to design.
Describe the reason why ?
2. The substrate of nMOS transistor must be connected to ground, while the
substrate of pMOS transistor must be connected to VDD, power supply.
Describe the reason why ?
3. What decide the maximum LSI speed or clock frequency ?
4. Describe the difference between Digital LSI and Analog LSI.
5. What is the reason why LSI manufacturing requires volume production ?
6. Why LSI costs are decided by chip area ?
7. Why LSI reliability is much more than the discrete circuits ?
8. Why place and rout affects the performance of LSI ?
9. CMOS process is preferred to NMOS process or Bipolar process. Describe the
reason.
10. What is the role of the stray or parasitic capacitance ?
2.VLSI Basic 1
[1] The nMOS pull down logic gates blocks are shown in
the figure.
1.Draw the complete CMOS circuit.
A
2.Derive the logic function.
3.Draw the stick diagram layout of the CMOS circuit.
4.Draw the complete pseudo-NMOS circuit by adding a B
pMOS transistor.
5.Draw the complete CMOS domino logic to achieve the
C
same logic function.
6.Derive the channel width and length of CMOS gate,
which has the same characteristics in terms of rise and
fall times as a CMOS inverter consisting of nMOS of
W/L=250/25 and pMOS of W/L = 400/25.
A
B
2.VLSI Basic 2
[2] Figure shows Gate Array layout mask patterns, which consists of
basic cells. Basic cell is a identical transistor cell. Gate Array employs only
metal and its contact window masks over the pre-manufactured
Transistor array.
1.Describe basic cell.
2.Derive the circuit of the figure.
3.Show the width and length of transistor used in the figure.
4.Describe functional behavior of the circuit.
5.This circuit is used as shown in figure. Describe the function of this circuit.
data_input
O ut_P
O ut_B uffer
図 １．１
O ut_N
input_M ode
2.VLSI Basic 2
data_input
input_M ode
O ut_P
O ut_N
Gate Delay
CMOS Driver sends signal
through wire to 10 CMOS
Gates. Calculate gate delay of
the driver without and with
wire delays.
Wire unit resistance is
Rline=500 Ω/mm、wire unit
capacitor is Cline=300fF/mm.
CMOS Inverter has On
Resistance Ro/W and output
and input capacitor CoW for
channel width of W/25nm,
where Ro is 200 Ωum,
Co=50fF/um. VDD=1.0V,
VT=0.4V
wire Delay
3.Standard Cell Overview
Standard Cell Design has many advantages over another design.
1. Layout design can automatically be performed by CAD tool.
Describe the reason.
2. Logic Synthesis can also be performed with excellent design
compiler. In order to run logic synthesizer, what data of
standard cells are needed ?
3. What is a major requirement for each standard cell ?
On the other hand, standard cell design is not optimal solution, in
terms of design optimization.
1. Describe the reason why the designed schematic circuits are
not optimal in terms of power, speed, and chip area.
2. Gate Array is a semi custom design so that wefa can be
fabricated in prior to design requirement. Describe the reason why
standard cell is not semi custom design in the same sense as Gate
Array.
4. Verilog HDL
Describe both data path and
control circuit of Figure by
VerilogHDL.
After the starting signal S
raises, the circuit of Figure
accepts a sequence of input
data and accumulates them.
5. Logic Design
Consider logic function
F=ab’cd+ab’e+b’d’e+f
1) Find out kernel and its cofactor of the logic function.
2) Show the algebraic division by selecting one of kernels.
3) Repeat until no further division is made.
5. Logic Design
D 0 Q0
X0
Y0
D 1 Q1
X1
Y1
D2 Q1
Combinatorial
Logic
Circuit
Y2
X2
Input X
[1] Consider to design Standard Cell LSI for Figure 1.
While, Table 1 shows the specification or the truth
table of combinatorial circuit Fc, which is a subsystem
of the state machine Sm as shown in Figure 1.
1. Describe the state transition graph of the state machine
Sm.
2. Describe 4 outputs of the combinatorial circuit Fc by logic
equations.
3. Derive kernels and their cofactors of each logic function of
the combinatorial circuit Fc.
4. Do logic synthesis for the combinatorial circuit Fc and
draw the logic circuit.
5. Suppose that we have only cells such as 3 input NAND,
AND-OR-Inverters and so on in standard cell library.
Please perform technology mapping for the logic circuit of
the combinatorial circuit Fc.
Output Y
Y3
X3
Q 2 Q 1 Q0 X D 2 D 1 D 0 Y
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
*
0
0
0
1
0
1
0
*
0
0
0
1
0
1
1
*
0
0
1
1
1
0
0
*
1
1
0
0
1
0
1
*
0
0
0
1
1
1
0
*
1
1
1
1
1
1
1
*
0
1
1
1
6. Describe VerilogHDL for this state machine Sm.
7. Suppose that we do simulation of the state machine in order to
verify correctness of your VerilogHDL, Draw the timing chart of
the machine Sm. Assume that clock frequency is 100MHz and
gate delay of each cell is 3 nsec and FF works with no delay.
8. By deriving Binary Decision Diagram (BDD), perform formal
verification for the derived logic circuit of the combinatorial
circuit Fc as follows.
9. 5.1) Derive BDD from the truth table 1.
10. 5.2) Derive BDD for 3input-NAND and AOI(AND-OR Inverter)
from the derive circuit of the combinatorial circuit Fc.
11. Describe scan path design for the state machine of Figure 1 and
describe how to test the state machine with scan path.
12. Describe why this scan path design is necessary.
6. Logic Verification
Perform formal verification of the above logic circuit using BDD
Representation.
Sum Generation Function
Carry Generation Function
Carry Generation Function
7. Placement
Q2'
X
2] Suppose that the derived circuit is shown as in
Figure 2.
Decide the placement of all gates in one row for
the circuit by using the model of standard cells as
shown in Fig.3.
Do the interconnection between those gates. The
number of horizontal tracks used in channel routing
should be minimized.
Describe the reason why, after layout, we should
perform again timing analysis.
Suppose that all gate delays are 1nsec and all
wire delays are 1nsec. Calculate the total delays on
critical path.
D2
Q1'
D1
Q0
D0
Q0'
Y
7. Layout Design
Suppose that above graph represents connections between different
Standard cells placed in a row. Find out the best placement of this
Standard cells.
7. Layout Design
1
9
10
7
13 10
3
5
6
4
3
8
11 12
0
8
13
2
9
1
5
5
7
0
3
11
6
4
8
12
2
11
Above figure shows routing channel with net number to be connected.
Net 0 indicates no connection.
(1) Try routing by left edge method.
(2) Draw a restriction graph, whose node corresponds to net, and
whose edge corresponds to the relationship of overlapping of area.
Module Test(clock, X);
Input clock, X;
output Y;
reg [1:0] current_state, next_state;
parameter s0=2’b00, s1=2’b01, s2=2’b11,
s3=2’b10;
always @(posedge clock)
current_state<=next_state;
always @(current_state or input)
begin
case(current_state)
s0: next_state<=X?s1:s0;
s1: next_state<=s2;
s2: next_state<=s3;
s3: next_state<=s0;
default:next_state<=s0;
endcase
end
always @(current_state or X)
begin
case(current_state)
s0: Y <=0;
s1: Y <=0;
s2: Y <=0;
s3: Y <=1;
default:output<=0;
endcase
end
endmodule
1. Describe the state transition diagram
2. Obtain the state transition table with
input (Q1, Q0, X) and output (D1, D0,
Y), where (Q1, Q0) are corresponding
to states s0-s3 and (D1, D0) are inputs
of FFs for (Q1, Q0) respectively.
3. Obtain the logic functions D1, D0, and Y,
respectively.
4. Describe the state machine by using
the combinational logic block with input
(Q1, Q0, X) and output (D1, D0, Y).
Q0
Q1 Q1 D0
D1 D-FF
Q1
Q1
Q0 Q0
D0 D-FF
X Q0 Q1 D0
Q0 Q1 Y
Q0
Q0
[4] 2 D-FFs, OR-AND and AND standard cells are shown in Figure 2 with
interconnection information.
1.Verify the net number on the terminal of 2 D-FFs and OR-AND and AND cells by
showing the routing between those cells in an upper channel routing area. Suppose
that the input comes from the left side and the out goes out to the right side in the
routing channel.
2.Place them in 1 dimensional row so as to minimize the number of tracks in routing
channel.
3.Please explain what is the clock tree insertion and explain the reason why clock
tree insertion should be conducted in between placement and routing procedure.
4.Show the optimal routing in an upper channel area to realize the state machine.