PSoC Designer
Module 1:
Introduction to PSoC
Module Outline
Section 1: Introduction to PSoC
Section 2: PSoC Designer™ IDE Software
Section 3: Hands-On Example Project
2
PSoC
An Introduction
What is a PSoC Mixed Signal Device?
P rogrammable
S ystem
on
C hip
PSoC combines:
• the familiarity of a microcontroller
• the configurability of an CPLD
• the capabilities of an Mixed –
Signal Array
4
What is PSoC?
PSoC
Devices
Features:
• Configurable Analog Blocks
• Implement ADCs, DACs, filters, amplifiers, comparators, etc.
• Configurable Digital Blocks
• Implement timers, counters, PWMs, UART, SPI, IrDA, etc.
• 4KB to 32KB of Flash memory for program storage
• 256B to 2KB of SRAM for data storage
• M8C Microcontroller: 4 Million Instructions Per Sec
5
What is PSoC?
Inputs
•
•
•
•
Each pin can sink 25mA
Programmable filters
Flexible sensor interface I/O
3 types of ADCs, up to 4
Processing
• Fast M8 Microcontroller Core
• Multiply Accumulate
Outputs
• Each pin can source 10mA
• Up to 16 PWMs, Timers, Counters
• Up to 9-bit DACs, 14-bit ADCs
Support Functions
•
•
•
•
6
EEPROM
Sleep Options
Watch Dog Timer
Low voltage detect
PSoC Die
BandGap
POR
GPIO
RAM
Dec.
M8 CPU
16k Flash
PUMP
SROM
MAC
32K Osc
PLL/Osc
CY8C27XXX – PSoC 1208
7
PSoC Architecture
I2C
I2C
Slave, Master,
Multimaster
System
Bus
M8C
CPU
Core
System
Clocking
Generator
BB
BB
CB
CB
UART
ADC
BB
BB
CB
CB
BB
BB
CB
CB
Port 5
BB
BB
PWM_16
CB
CB
Clocks
Analog PSoC Block Array
Interrupt
Controller
24 MHz
Internal
Oscillator
MAC Multiply
Accumulate (up to 2)
CT
CT
CT
CT
SC
SC
SC
SC
SC
FilterSC
SC
SC
ADC
LVD
Supervisor
Port 6
Programmable
Interconnect
and Logic
Analog Input
Muxing
Configurable I/O Ports
(Decimator)
Watchdog
Sleep Timer
SMP
Flash
Program
Memory
(up to
32K)
ADC
Decimator
Port 7
Digital PSoC Block Array
SRAM
Memory
(up to 2K)
Port 4
Port 3
Port 2
LCD
Analog Output
Drivers
Port 1
Port 0
8
Analog Functions (Subset)
•ADC
Incremental 6-14 bits
Delta Sigma 6-13 bits
•DAC
6, 8, and 9 bit
6 and 8 bit multiplying
•Filters
2-pole Low-pass
2-pole Band-pass
•DTMF Dialer
•Modulator
•Peak Detector
•V to I Converter
•Amplifiers
Programmable Gain
Instrumental
Inverting
•Comparators
Programmable
Hysteresis
Zero-Crossing
•CapSense
9
Digital Functions (subset)
•Timer
8, 16, 24, 32 bit
•Counter
8, 16, 24, 32 bit
•PWM
8, 16, 24, 32 bit
•Dead Band Generator
8, 16, 24, 32 bit
•Pseudo Random Source
•Cyclic Redundancy Check
•Communication Interface
I2C Master
I2C Slave
SPI Master
SPI Slave
Full Duplex UART
Tx, Rx
Full Speed USB v2.0
10
Interconnection Scheme
• Define connections
between pins and
function blocks
• Define connections
between function
blocks
• Define clock paths
• Change
connections
dynamically too!
11
User Modules
Pre-configured and Pre-characterized Digital
and Analog PSoC Blocks
Greatly simplifies and shortens coding process
Analogous to On-chip Peripherals
• ADCs, DACs, PGAs, Filters
• Timers, Counters, PWMs
• UART, SPI, I2C
Defines the Register Bits for Initial Configuration
Selected via Double Click in IDE
User Modules Include
• Application Programmer Interfaces (APIs)
• Interrupt Service Routines (ISRs)
• Specific UM Data Sheets
12
Additional Features
•
•
•
•
•
13
Comprehensive Design Tools
Intuitive Resource Placement
Easy Routing
Powerful Logic
Dynamic Reconfiguration
PSoC Design Tools
Free Design Software
• Device Editor
• Application Editor
• C Compiler
• Assembler
• Librarian
Graphical Application
• Debugger
Design Software……
No MCU Coding!
Low Cost ICE
• CY3215-DK
•Trace, Dynamic Event Point
• Every thing you need for
PSoC development
14
PSoC® Designer™ 5.0
A New Paradigm in Embedded Design
• An integration of PSoC software
• PSoC Express™ - a visual embedded code free design environment
• PSoC Designer 4.4 - a powerful and more traditional IDE
• MS Visual Studio based GUI—dock, tab, and float windows
• Upgraded Debugger; new “Run-to-Cursor” breakpoint features
EASY-TO-USE, FAST, FLEXIBLE
15
PSoC Designer 5.0
System-Level View (Formerly PSoC Express)
16
PSoC Designer 5.0
Chip-Level View (Formerly PSoC Designer 4.4)
17
PSoC Designer 5.0
System-Level to Chip-Level Transitions
Optimize the Design
Design & Build
3
1
4
2
Open Chip-View
18
Customize the Code
PSoC® Programmer™ 3.xx
Customize & Enhance your PSoC Programming Experience
•Customizable GUI—maximize & minimize what you want to see
•COM object architecture—open access to programmer functionality
•Automatic PSoC Programmable System on Chip Detection
•Accelerated prototyping—turn timely verification on/off as needed
•Huge array of GUI enhancements—cleaner, easier to use interface
Simple View
Classic View
Modern View
19
PSoC Programmer 3.xx
Classic View
20
PSoC Programmer 3.xx
Modern View
21
PSoC Programmer 3.xx
Simple View
22
Section 2: PSoC
Designer IDE
Software
Intuitive Placement
1) Drag Green “Target Placer” from
default location
2) Drag to desired location
(Target Placer box fills in green when place-able)
3) Press “Place User Module Button”
24
Easy GUI Routing
25
Powerful Combinational Logic
26
Powerful Combinational Logic
27
Dynamic Reconfiguration
More than meets the eye: Multiple Configurations
28
Integrated Development Environment
•
•
•
•
•
•
29
Device Editor
Application Editor
C Compiler
Assembler
Librarian
Debugger
PSoC Designer
Device Editor – Interconnect View
Placing User Modules
Global
resources table
User module
parameter table
UM
Workspace
User Module
window
Port table
30
• View block architecture with
combined UM & port views
• Generates routed block to
block schematic
• Routed global I/O connection
schematic
• Step through potential UM
placement options
• Select desired placement
option for UM
• Select UM and resource
interconnections
• Select/configure UM and
global device resources
• Define clocking for UMs
• Configure mode and drive
level for GPIO pins
PSoC Designer Application Editor
For Users to Write Code
For Users to Assemble/Compile Code
• View and edit individual
source files
• Set and remove
bookmarks (Editing tool)
• Assemble/compile
individual files
• Build entire project
including
assemble/compile* all
files in project
• Source line error pointer
* The C compiler needs to be enabled for use.
31
PSoC Designer C Compiler
The C compiler by Hi Tech is an optional component of the
PSoC Designer IDE. Once enabled, it is fully integrated
into the IDE and allows PSoC Designer to support C
source level debugging.
Features Include:
• ANSI C Compiler
• Supports Inline Assembly and can interface with Assembly
Modules
• Integrated code compressor
• Modern Stack-Based Architecture
• 7 Basic Data Types Including IEEE 32-Bit Floating Point
• Assembler and Linker
• Math and String Libraries
• C Interrupt Service Routines
• Librarian
For more info on the C compiler, please see the C language compiler user guide in the
documentation folder of PSoC Designer.
32
PSoC Designer Debugger
• Interface to ICE
• View contents of Register
and Memory spaces
• Change the contents of the
register banks and the RAM
• Run/Halt /Single Step
• Set breakpoints and event
points
• Capture trace
Note: We will not be using the DeBugger during this workshop
33
PSoC Hands On
Example Project
PSoC Design Flow
• Determine system requirements
• Choose User Modules
• Place User Modules
• Set global and User Module parameters
• Define the pin-out for the device
• Generate the application
• Review generated code
• Demonstrate working configuration
35
Project Requirements
Blink two LEDs at approximately 2Hz, with duty
cycle of 40% and 20%
Implementation:
Create An MCU with Two Pulse Width Modulators:
• Select Two PWM User Modules
• Set the PWM parameters
• Initialize the global clocks
• Connect the PWM outputs to the PSoC Pup LEDs
36
Project Implementation
Pup
PSoC
16-bit
PWM
÷ 65535
÷16
P2[0]
(94kHz)
(1.5MHz)
24MHz
(1.4Hz)
÷16
VC1
VC2
16-bit
PWM
÷ 65535
37
P2[1]
(1.4Hz)
Starting a New Project
• Open PSoC Designer
• Select Start new
project
38
Starting a New Project
• Select
Project Type
• Name The
Project
39
Starting a New Project
• Select Device and
Coding Method
• CY8C29466-24PXI
• C
• OK
40
Select and Place User Modules
Select the PWM16 from
the User Modules page
Place User Modules for this Project
• How do I know where to place the User
Modules?
• How does PSoC Designer help me?
41
Place User Modules
Try-out the modules individually first
• See how restrictive they are, then return to original location
PSoC Designer will only allow the modules to be placed where
the chip can support them
PSoC Designer will not prevent a placement that may create a
conflict for resources
• Example: If you have an ADC and temperature sensor, they both
use the comparator bus. There is only one comparator bus per
column, therefore these two UMs must reside in separate
columns in order to be used simultaneously.
Read the UM Data Sheets for details
Use the Cypress Online Resources
• www.cypress.com/support
42
Place User Modules
Place the two selected User Modules. Double Click on
PWM16 wait a few moments until the user module is
placed in the Interconnect Window - repeat
PWM16_1 – Digital Blocks DBB00/DBB01
PWM16_2 – Digital Blocks DBB10/DBB11
Recommend placing the PWMs in the Basic Digital Blocks to
Save the Digital Communication Blocks
43
Place User Modules
• When you are done the screen should look like this
44
Configure Global Resources
Power Setting: 5.0V/24MHz
CPU_Clock: SysCLK/2 (12MHz)
32K_Select: Internal
• Not using an external crystal
PLL_MODE: Disable
• PLL can only be enabled when
32K_Select is External (crystal)
Sleep_Timer: 512_Hz. (Default)
VC1 = SysClk/N: Set to 16
• This divides 24MHz by 16 =
1.5MHz
VC2 = VC1/N: Set to 16
• This divides the 24V1 by 16
(1.5MHz/16=94kHz)
VC3 Source: SysClk/1
VC3 Divider: 1
45
Configure Global Resources
SysClk Source: Internal
SysClk*2 Disable: YES
Analog Power: SC On/Ref Low
This is required to power up any of the analog blocks,
depending on the number of analog functions. A Ref Med or
Ref High may be required (and will increase power
consumption)
Ref MUX: (Vdd/2) ±Bandgap (default)
AGndBypass: Disabled
46
Configure Global Resources
Op-Amp Bias: Low (default)
This is not recommended as anything but low
A_Buff_Power: Low (default)
Adequate for most projects
This selects the power level of the analog output buffer
There is a tradeoff between drive output
power and power consumption.
SwitchModePump: OFF
Trip Voltage [LVD (SMP)]: 4.64V (5.0V)
47
Configure User Modules
•PWM16_1: We want to generate a 1/5 duty cycle
•User module parameters can be configured in two ways: through
the GUI or through the User Module Parameters window. In this
class we will use the User Module Parameters window in the left
bottom corner.
Set Clock to VC2 (94kHz)
Set Enable High to keep the PWM always running
Set CompareOut to Row_0_Output_0
Set TerminalCountOut to None
Set Period to 65535 (1.4Hz)
Set PulseWidth to 13107
Compare Type Less Then Or Equal
Interrupt Type Terminal Count
ClockSync to Sync to SysClk
InvertEnable set to Normal
48
Configure User Modules
PWM16_2: We want to generate a 2/5 duty cycle
Set Clock to VC2 (94kHz)
Set Enable High to keep the PWM always running
Set CompareOut to Row_1_Output_1
Set TerminaCountOut to None
Set Period to 65535 (1.4Hz)
Set PulseWidth to 26214
Compare Type Less Then Or Equal
Interrupt Type Terminal Count
ClockSync to Sync to SysClk
InvertEnable set to Normal
49
Interconnect Blocks to Resources
What interconnection possibilities are there?
• Data Inputs
• Data Outputs
• Clocks
• Block-to-block
When you specify a PSoC block connection to a
pin you are making a physical connection to the
hardware of the PSoC device.
50
Define the Pin-out
What pins need to be defined?
• UM Inputs
• UM Outputs
• General Purpose IO
What happens as pins are defined?
Pin-out our project
• LEDs
51
Interconnect Blocks to Resources
Route PWM16_1 to pin:
• Connect PWM16_1 output to Row_0_Output_0
• Connect Row_0_Output_0 to GlobalOutEven_0
Left Click
52
Left Click
Interconnect Blocks to Resources
Route PWM16_1 output to pin
• Port 2 is connected to the LEDs on the Pup board
53
Interconnect Blocks Resources
Route PWM16_2 output to pin
54
Interconnect Blocks Resources
Route PWM16_2 output to pin
55
Configuration Complete!
Save project – Go to File tab
Now what? Where are we?
Time to “Generate Application”
• All settings used by PSoC Designer
to create the boot-up code to configure
the registers at reset
• ISRs are created (but not updated)
• APIs are created or updated
• Device Data Sheet generated
You must Generate Application whenever changes are made
to the configuration
Now switch to the Application Editor view
56
Time to Create Application Code
PSoC Designer generates application code
based on the configurations you just
defined in the Device Editor.
Project File Tree, located to the left of the
application window, contains:
• all interrupt routines
• header files
• include files
• configuration tables
All APIs and ISRs can be modified by the
user.
57
Create Application Code
Open the main.c file
Type the PWM start commands for each PWM_1 and PWM_2
void main()
{
// Insert your main routine code here.
PWM16_1_Start () ;
PWM16_2_Start () ;
while (1);
}
58
Create Application Code
59
Build Project
Assembles code, links, and locates
Can individually assemble files as well
Explore Application Editor Features
• Project file management (view/add/delete files)
• Finding compilation errors
60
Program The Device
61
Program The Device
Select MINIProg in the
port window
Select Connect
Select Program
When Programming
is complete Toggle
Device Power
Congratulations, you
have just completed
your first PSoC
design!
62
Appendix
63
SCBlock Amplifier Examples
•Bi-Directional Current Source
Vset
DAC6
•DiffAmp configured with gain of one.
• CF=CB=CA=16
• Sign = Pos
•External Resistor and DAC value sets
current.
• Independent of load.
Vout  Vload  Vset
Vout  Vload
Vset
i

Rset
Rset
64
DiffAmp
Vload
-B
P2.1
x1
Buf0
P0.3
+A
Rset
i = -Vset / Rset
Rload
Vout
SCBlock Filters FilterCalc
• Enter Following Parameters
• Rolloff Frequency (f0)
• Acceptable Tolerance
• Damping Value
• Acceptable Tolerance
• Column Clock (fs *4)
FilterCalc generates all Capacitor values
that meet these requirements.
 Output file readable with Excel.
 43 different solutions for this particular
example.
65
SCBlock Low Pass Filter
• Programmable
• Roll off frequency (f0)
• Damping ratio
• Gain
• 300 Hz to 250 kHz
• Scaled to clock
C2
 
C4
CA
Vin


66

C1

CB


C3



Vout
 s
1  
 2 fS
2



Vout
C
 1
Vin
C2  s  2  C C
1 1 C4  s C4
   A B  
 
1
f
C
C
4
2
C
f
C
2 
s
2 s
 s  2 3
SCBlock as Comparator
•Two Cap Comparator
•With feedback capacitor CF
removed Vout goes to either
the high or low rail.
• Vout goes high when
VinACA > VinBCB
• Vout goes low when
VinACA < VinBCB
•VinB is the inverting input
input.
67
2
CB
1
1
CA
VinB
VinA
2
1
Vout
SCBlock as Integrator
•SCBlock Integrator
•Uses standard gain stage with the
exception that the switch to
discharge CF has been disabled.
•So:
Vout  Voutold
CA
 Vin
CF
Vout  C A  1
 
  f s
Vin  CF  s
68
1
CF 2
1
Vin
CA
2
s  2f 1
Vout
SCBlock as Integrator
Single Pole LPF
•Dual Input SC Integrator
1
•Feedback makes low pass filter
with gain.
• Ratio of CA & CB determines
gain.
• CF,CB, and fs determines rolloff
frequency.
•Setting Vin to Vref makes filter DAC.
• Much higher fs than Conventional
DAC
Vout  C A 
1
  
Vin  CB 
s  CF 1 
1  
 
f s  CB 2 
69
CF 2
1
Vin
CA
2
2
CB
1
buf
Vout
SCBlock as Integrator
Power Driver
•Dual Input SC Integrator
•External Emitter follower
makes a high power output
driver.
1
• Able to drive all the way to Vss
1
rail
Vin
CF 2
CA
buf
2
Vout
2
CB
1
70
Vcc
Rload
SCBlock as Integrator
Speaker Driver
•Dual Input SC Integrator
1
•Or a 4 Ohm Class B Speaker
Driver.
1
Vin
CF 2
CA
2
4 Ohm
CB
71
buf
Vout
2
1
Vcc
SCBlock as 2 Pole Filter
• Two Pole Filters
• Constructed with a BiQuad Circuit Topology
• Continuous Time Implementation shown below
• Requires Three Op Amps
• Middle one only used to change polarity
R2
C4
CP
V in
CB
CA
R
R1
R3
R
CPP
2
Vout
R2 s R1R3C AC pp  sR1C p  1
  2
Vin
R1 s R2 R3C ACB  sR2C4  1
72
V out
SCBlocks as 2 Pole Filter
• Two Pole Filters
• Switched Capacitor Implementation
• Requires Only Two Op Amps
C2
 
C4
CP
Vin

CA

C1


CB


C3


Vout

CPP
Vout
Vin
73
s 2  C AC pp 1 C p 1  s  C p  C1

 

   
2 
CC
2 C2 4  f s  C2  C2
f
  s 2 2 3
s  C AC B 1 C 4 1  s  C 4 


      1
2 
C
C
2
C
4  f s  C2 
fs  2 3
2
High Pass
Band Pass
Low Pass
SCBlock Band Pass Filter
• Programmable
• Center frequency (fc)
• Q
• Gain
• 300 Hz to 250 kHz
• Scaled to clock
C2
 
C4
CB
CA
Vin




C1


C3


Vout
AnalogBus
CompBus
74
Vout
Vin
s CB 
s 
1 

f s C3  2 f S 
C
 1
C 2 s 2  C AC B 1 1 C 4  s C 4

 
 
1
f s  C 2 C3 4 2 C 2  f s C 2
Elliptical Low Pass Filter
• Combines High Pass
• and Low Pass Filters
2
Vout
C
 1
Vin
C2 


• Produces two zeros.
• Low pass filter when:
f0lo wp a ss  f0h ig h p a ss
C2
 
C4
CA
Vin



CPP
75

C1
CB


C3



Vout
 s  C C
1
1     PP A  
 f s   C1C3 4 
2
s   C AC B 1 1 C 4  s C 4
 
 
 
1
f s   C2C3 4 2 C2  f s C2
SCBlock Notch Filter
• Special Case of
• Elliptical Low Pass
• Filter where:
2
Vout
C
 1
Vin
C2 


f0lo wp a ss  f0h ig h p a ss
C2
 
C4
CA
Vin



CPP
76

C1
CB


C3



Vout
 s  C C
1
1     PP A  
 f s   C1C3 4 
2

s  C AC B 1 1 C 4  s C 4
 

 
1
f s   C2C3 4 2 C2  f s C2