ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 22: October 31, 2011
Pass Transistor Logic
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Previously
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Two Xor Gates
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Today
• Pass Transistor Circuit
– Output levels
– Cascading
• Series pass transistors?
• Delay
• Transmission gates
• Tristate gates
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Cascading Pass Transistors
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Chain without Inverters
• What if we did this?
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Extract key path
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t=0 (after Vin transition 10)
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t=4t (after Vin transition 10)
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t=∞ (after Vin transition 10)
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Focus on Pass tr
• Vgs?
• Operation mode?
• Current flow?
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Voltage of Chain
• What is voltage at output?
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How compare
• Compare
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DC Analysis
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DC Analysis – chain of 6
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Conclude
• Can chain any number of pass
transistors and only drop a single Vth
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Capacitance
• What is Capacitance per stage (@y)?
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Delay
• Delay as a function of chain length?
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Compare
• CMOS
• Buffered Pass TR
• Unbuffered Pass TR
• Delay
• Area
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Pass TR Tree
• What if we did this?
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Path
• What’s different about this?
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Gate Cascade?
• What are voltages?
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Demonstration Circuit
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SPICE
• TODO show spice results of voltages
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Demonstration Chain
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Spice
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Conclude
• Cannot cascade degraded inputs into
gates.
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Pass Rail-to-Rail
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Transmission Gate
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Bus Drivers
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Tristate Driver
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Tri-State Drivers
Admin
• Project
– Due Friday
• Midterm 2: Nov. 9th
– Week from today in the evening
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Midterm Topics
• Scaling
• Tau-model
– Estimation and
optimization
• Elmore-delay
– Estimation and
optimization
• Energy and power
– Estimation and
optimization
• Logic
– CMOS
– Ratioed
– Pass transistor
• No clocking
– Except to motivate
delay targets and
power calculations
Note: 2010 midterm Q4 – Cdiff, trans gates, Elmore, opt.
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Idea
• There are other circuit disciplines
• Can use pass transistors for logic
– Even chains of pass transistors
– Sometimes gives area or delay win
• Do not cascade as easily as CMOS
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