ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 13: October 6, 2010
Scaling
1
Penn ESE370 Fall2010 -- DeHon
Today
• VLSI Scaling Trends/Disciplines
• Effects
• Alternatives (cheating)
2
Penn ESE370 Fall 2010 -- DeHon
Scaling
• Premise: features scale “uniformly”
– everything gets better in a predictable
manner
• Parameters:
 l (lambda) -- Mead and Conway (Day12)
 F -- Half pitch – ITRS (F=2l)
 S – scale factor  Rabaey
 F’=s×F
3
Penn ESE370 Fall 2010 -- DeHon
ITRS Roadmap
• Semiconductor Industry rides this
scaling curve
• Try to predict where industry going
– (requirements…self fulfilling prophecy)
• http://public.itrs.net
4
Penn ESE370 Fall 2010 -- DeHon
MOS Transistor Scaling
(1974 to present)
S=0.7
[0.5x per 2 nodes]
Pitch
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Penn ESE370 Fall 2010 -- DeHon
Gate
[from Andrew Kahng]
5
Half Pitch (= Pitch/2) Definition
Metal
Pitch
(Typical
DRAM)
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Penn ESE370 Fall 2010 -- DeHon
Poly
Pitch
(Typical
MPU/ASIC)
[from Andrew Kahng]
6
Node Cycle Time:
0.7x
0.7x
Log Half-Pitch
Scaling Calculator +
1994 NTRS .7x/3yrs
Actual .7x/2yrs
Linear Time
250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16
0.5x
N
N+1
Node Cycle Time
(T yrs):
N+2
*CARR(T) =
[(0.5)^(1/2T yrs)] - 1
* CARR(T) = Compound Annual
Reduction Rate
(@ cycle time period, T)
Source: 2001 ITRS - Exec. Summary, ORTC Figure
Penn ESE370 Fall 2010 -- DeHon
CARR(3 yrs) = -10.9%
CARR(2 yrs) = -15.9%
[from Andrew Kahng]
7
Scaling
•
•
•
•
•
Channel Length (L)
Channel Width (W)
Oxide Thickness (Tox)
Doping (Na)
Voltage (V)
8
Penn ESE370 Fall 2010 -- DeHon
Full Scaling
•
•
•
•
•
Channel Length (L)
S
Channel Width (W)
S
Oxide Thickness (Tox) S
Doping (Na)
1/S
Voltage (V)
S
9
Penn ESE370 Fall 2010 -- DeHon
Effects on Physical Properties?
•
•
•
•
•
•
•
•
Area
Capacitance
Resistance
Threshold (Vth)
Current (Id)
Gate Delay (tgd)
Wire Delay (twire)
Power
• Go through full
(ideal)
• …then come back
and ask what still
makes sense today.
10
Penn ESE370 Fall 2010 -- DeHon
Area
 l  lS
 A=L×W
 A  AS2
 130nm  90nm
 50% area
 2× capacity same
area
L
S=0.7
[0.5x per 2 nodes]
Pitch
W
Gate
11
Penn ESE370 Fall 2010 -- DeHon
Capacity Scaling from Intel
12
Penn ESE370 Fall 2010 -- DeHon
ITRS 2009 Moore’s Law
13
Penn ESE370 Fall 2010 -- DeHon
Capacitance
• Capacitance per unit
area
– Cox= eSiO2/Tox
– Tox S×Tox
– Cox  Cox/S
14
Penn ESE370 Fall 2010 -- DeHon
Capacitance
• Gate Capacitance
 Cgate= A×Cox
 A  A×S2
 Cox  Cox/S
 Cgate 
S×Cgate
15
Penn ESE370 Fall 2010 -- DeHon
Threshold Voltage
• VTH S×VTH
16
Penn ESE370 Fall 2010 -- DeHon
Current
• Saturation Current
Id=(mCOX/2)(W/L)(Vgs-VTH)2
Vgs=V S×V
VTH S×VTH
W S×W
L S×L
Cox  Cox/S
Id S×Id
17
Penn ESE370 Fall 2010 -- DeHon
Gate Delay
 tgd=Q/I=(CV)/I
 V S×V
 Id  S×Id
 C  S×C
 tgd  S×tgd
18
Penn ESE370 Fall 2010 -- DeHon
Overall Scaling Results, Transistor Speed and Leakage. Preliminary Data
from 2005 ITRS.
•HP = High-Performance Logic
•LOP = Low Operating Power Logic
•LSTP = Low Standby Power Logic
Leakage Current
Intrinsic Transistor
Delay, t = CV/I
10.00
(HP: standby power
dissipation issues)
(lower delay = higher speed)
1.E+00
HP
LOP
1.E-01
LSTP
1.00
CV/I (ps)
(ps)
Isd,leak (uA/um)
1.E-02
LSTP Target:
Isd,leak ~ 10 pA/um
1.E-04
0.10
HP Target:
17%/yr, historical
rate
0.01
2005
LOP
1.E-03
2007
2009
2011
2013
2015
17%/yr
rate
2017
1.E-05
Planar Bulk
MOSFETs
1.E-06
2005
2019
2007
2009
2011
Advanced
MOSFETs
2013
2015
Calendar year
Calendar Year
19
2017
2019
ITRS 2009 Transistor Speed
RO=Ring
Oscillator
20
Penn ESE370 Fall 2010 -- DeHon
Resistance
• R=rL/(W*t)
• W S×W
• L, t similar
• R  R/S
21
Penn ESE370 Fall 2010 -- DeHon
Wire Delay
 twire=RC
 R  R/S
 C  S×C
 twire  twire
• …assuming (logical)
wire lengths remain
constant...
• Assume short wire or
buffered wire
• Important cost shift
we will have to watch
22
Penn ESE370 Fall 2010 -- DeHon
Power Dissipation (Dynamic)
• Capacitive
(Dis)charging
 P=(1/2)CV2f
 V S×V
 C  S×C
 P S3×P
• Increase
Frequency?
 tgd  S×tgd
 So: f  f/S ?
 P  S2×P
23
Penn ESE370 Fall 2010 -- DeHon
Effects?
•
•
•
•
•
•
•
•
Area
S2
Capacitance
S
Resistance
1/S
Threshold (Vth)
S
Current (Id)
S
Gate Delay (tgd) S
Wire Delay (twire) 1
Power
S2S3
24
Penn ESE370 Fall 2010 -- DeHon
Power Density
• P S2P (increase frequency)
• P S3P (dynamic, same freq.)
• A  S2A
• Power Density: P/A
– P/A  P/A increase freq.
– P/A  S×P/A same freq.
25
Penn ESE370 Fall 2010 -- DeHon
Cheating…
• Don’t like some of the implications
– High resistance wires
– Higher capacitance
– Atomic-scale dimensions
• …. Quantum tunneling
– Need for more wiring
– Not scale speed fast enough
26
Penn ESE370 Fall 2010 -- DeHon
Improving Resistance
•
•
•
•
R=rL/(W×t)
W S×W
L, t similar
R  R/S
Don’t scale t quite as fast  now taller than wide.
Decrease r (copper)
27
Penn ESE370 Fall 2010 -- DeHon
28
Penn ESE370 Fall 2010 -- DeHon
Capacitance and Leakage
• Capacitance per unit
area
– Cox= eSiO2/Tox
– Tox S×Tox
– Cox  Cox/S
Reduce Dielectric Constant e (interconnect)
and Increase Dielectric to substitute for scaling Tox
(gate quantum tunneling)
Penn ESE370 Fall 2010 -- DeHon
29
ITRS 2009
Table PIDS3B Low Operating Power
Technology Requirements
Grey cells delineate one of two time periods: either before
initial production ramp has started for ultra-thin body fully
depleted (UTB FD) SOI or multi-gate (MG) MOSFETs, or
beyond when planar bulk or UTB FD MOSFETs have reached
the limits of practical scaling (see the text and the table notes
for further discussion).
2009 2010 2011 2012 2013 2014 2015 2016 2017
Year of Production
MPU/ASIC Metal 1 (M1) ½ Pitch (nm)
(contacted)
54
Lg: Physical Lgate for High Performance logic
(nm)
29
Lg: Physical Lgate for Low OperatingPower
(LOP) logic (nm) [1]
32
EOT: Equivalent Oxide Thickness (nm) [2]
Extended planar bulk
1
UTB FD
MG
Gate poly depletion (nm) [3]
Bulk
0.27
Channel doping (E18 /cm3) [4]
Extended Planar Bulk
3
Junction depth or body Thickness (nm) [5]
Extended Planar Bulk (junction)
14
UTB FD (body)
MG (body)
EOTelec: Electrical Equivalent Oxide Thickness (nm) [6]
Extended Planar Bulk
1.64
UTB FD
MG
Penn ESE370 Fall 2010 -- DeHon
2018
2019
2020
2021
2022
2023
2024
45
38
32
27
24
21
18.9
16.9
15
13.4
11.9
10.6
9.5
8.4
7.5
27
24
22
20
18
17
15.3
14
12.8
11.7
10.7
9.7
8.9
8.1
7.4
29
27
24
22
18
17
15.3
14
12.8
11.7
10.7
9.7
8.9
8.1
7.4
0.9
0.9
0.85
0.8
0.9
0.85
0.8
0.8
0.75
0.8
0.7
0.75
0.73
0.7
0.7
0.65
0.65
0.6
0.6
0.27
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3.7
4.5
5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
13
11.5
10
9
7
6.2
6
8
5.1
7.6
4.7
7
6.4
5.8
5.4
4.8
4.4
4.2
4
1.2
1.2
1.15
1.2
1.1
1.15
1.13
1.1
1.1
1.05
1.05
1
1
1.53
1.23
1.18
1.14
1.3
1.25
30
High-K dielectric Survey
Wong/IBM J. of R&D, V46N2/3P133--168
Penn ESE370 Fall 2010 -- DeHon
31
Intel NYT
Announcement
• Intel Says Chips Will Run Faster,
Using Less Power
– NYT 1/27/07, John Markov
– Claim: “most significant change in the
materials used to manufacture silicon chips
since Intel pioneered the modern integratedcircuit transistor more than four decades ago”
– “Intel’s advance was in part in finding a new
insulator composed of an alloy of
hafnium…will replace the use of silicon
dioxide.”
32
Penn ESE370 Fall 2010 -- DeHon
Wire Layers = More Wiring
33
Penn ESE370 Fall 2010 -- DeHon
Typical chip cross-section illustrating
hierarchical scaling methodology
Penn ESE370 Fall 2010 -- DeHon
[ITRS2005 Interconnect Chapter]
34
Improving Gate Delay
 tgd=Q/I=(CV)/I
 V S×V
 Id=(mCOX/2)(W/L)(Vgs-VTH)2
 Id  S×Id
 C  S×C
 tgd  S×tgd
Penn ESE370 Fall 2010 -- DeHon
Lower C.
Don’t scale V.
Don’t scale V:
VV
II/S
tgd  S2×tgd
35
…But
Power Dissipation (Dynamic)
• Capacitive
(Dis)charging
 P=(1/2)CV2f
 V V
 C  S×C
 P S×P
• Increase
Frequency?
 f  f/S2 ?
 P  P/S
If not scale V, power dissipation not scale down.
36
Penn ESE370 Fall 2010 -- DeHon
…And Power Density
• P P/S (increase frequency)
• P S×P (same freq.)
• But… A  S2×A
• P/A  (1/S3)P/A …. (1/S)P/A
• Power Density Increases
…this is where some companies have gotten into trouble…
37
Penn ESE370 Fall 2010 -- DeHon
Intel on Power Challenge
38
Penn ESE370 Fall 2010 -- DeHon
[source: Borkar/Intel, Micro37, 12/04]
ITRS Vdd Scaling:
V Scaling more slowly than F
39
DeHon-Workshop FPT 2009
CV2 scaling from ITRS:
More slowly than (1/F)2
40
DeHon-Workshop FPT 2009
Origin of Power Challenge
• Transistors per chip
grow at Moore’s
Law rate = (1/F)2
• Energy/tr must
decrease at this rate
to keep constant
• E/tr  CV2f
41
DeHon-Workshop FPT 2009
Historical Power Scaling
DeHon-Workshop FPT 2009
[Horowitz et al. / IEDM 2005]
42
Impact
• Can already place more transistors on a
chip than we can afford to turn on.
• Power potential challenge/limiter for all
future chips.
43
Penn ESE534 Spring2010 -- DeHon
What Is A “Red Brick” ?
• Red Brick = ITRS Technology Requirement
with no known solution
• Alternate definition: Red Brick = something
that REQUIRES billions of dollars in R&D
investment
Penn ESE370 Fall 2010 -- DeHon
[from Andrew Kahng]
44
The “Red Brick Wall” - 2001 ITRS vs 1999
Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876
Penn ESE370 Fall 2010 -- DeHon
[from Andrew Kahng]
45
ITRS 2009
Year of Production
MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted)
Lg: Physical Lgate for High Performance logic (nm)
Lg: Physical Lgate for Low OperatingPower (LOP) logic (nm) [1]
EOT: Equivalent Oxide Thickness (nm) [2]
Extended planar bulk
UTB FD
MG
Gate poly depletion (nm) [3]
Bulk
Channel doping (E18 /cm3) [4]
Extended Planar Bulk
Junction depth or body Thickness (nm) [5]
Extended Planar Bulk (junction)
UTB FD (body)
MG (body)
EOTelec: Electrical Equivalent Oxide Thickness (nm) [6]
Extended Planar Bulk
UTB FD
MG
Cg ideal (fF/mm) [7]
Extended Planar Bulk
UTB FD
MG
Jg,limit: Maximum gate leakage current density (A/cm2) [8]
Extended Planar Bulk
UTB FD
MG
Vdd: Power Supply Voltage (V) [9]
Bulk/UTB FD/MG
Vt,sat: Saturation Threshold Voltage (mV) [10]
Extended Planar Bulk
UTB FD
MG
Isd,leak (nA/mm) [11]
Bulk/UTB FD/MG
Mobility enhancement factor due to strain [12]
Bulk/UTB FD/MG
Effective Ballistic Enhancement Factor, Kbal [13]
Bulk/UTB FD/MG
Rsd: Effective Parasitic series source/drain resistance (Ω-µm) [14]
Extended Planar Bulk
UTB FD
MG
Id,sat: NMOS Drive Current with series resistance (µA/µm) [15]
Extended Planar Bulk
UTB FD
MG
Cg fringing capacitance (fF/mm) [16]
Extended Planar Bulk
UTB FD
MG
Cg,total: Total gate capacitance for calculation of CV/I (fF/µm) [17]
Extended Planar Bulk
UTB FD
MG
τ =CV/I: NMOSFET intrinsic delay (ps) [18]
Extended Planar Bulk
UTB FD
MG
Penn ESE370 Fall 2010 -- DeHon
2009
54
29
32
2010
45
27
29
2011
38
24
27
2012
32
22
24
2013
27
20
22
2014
24
18
18
2015
21
17
17
2016
18.9
15.3
15.3
2017
16.9
14
14
2018
15
12.8
12.8
2019
13.4
11.7
11.7
2020
11.9
10.7
10.7
2021
10.6
9.7
9.7
2022
9.5
8.9
8.9
2023
8.4
8.1
8.1
2024
7.5
7.4
7.4
1
0.9
0.9
0.85
0.8
0.9
0.85
0.8
0.8
0.75
0.8
0.7
0.75
0.73
0.7
0.7
0.65
0.65
0.6
0.6
0.27
0.27
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
3.7
4.5
5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
14
13
11.5
10
9
7
6.2
6
8
5.1
7.6
4.7
7
6.4
5.8
5.4
4.8
4.4
4.2
4
1.2
1.2
1.15
1.2
1.1
1.15
1.13
1.1
1.1
1.05
1.05
1
1
0.483
0.483
0.46
0.441
0.439
0.42
0.39
0.366
0.334
0.32
0.292
0.28
0.255
170
170
180
180
200
200
220
230
260
280
310
280
310
1.64
0.67
86
1.53
0.655
95
1.23
0.744
100
1.18
0.708
110
1.14
1.3
0.669
0.587
140
140
1.25
0.508
150
0.95
0.95
0.85
0.85
0.8
0.8
0.75
0.75
0.7
0.7
0.65
0.65
0.6
0.6
0.6
0.6
428
436
407
419
421
311
317
320
288
323
294
327
297
299
299
297
300
304
311
316
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1
1
1
1
1.06
1.12
1.19
1.26
1.34
1.42
1.5
1.59
1.69
1.79
1.9
2.01
220
200
170
160
150
170
165
160
160
150
160
150
150
150
150
150
140
140
130
130
984
1,070
1,080
1,120
1,050
1,100
1,190
1,130
1,210
1,140
1,200
1,320
1,370
0.176
0.186
0.169
0.179
0.17
0.18
0.181
0.181
0.182
0.179
0.18
0.179
0.18
0.66
0.669
0.63
0.62
0.61
0.6
0.571
0.547
0.516
0.499
0.472
0.5
0.47
0.43
0.41
0.4
0.38
0.33
0.31
0.28
0.26
0.23
700
0.243
0.913
1.24
746
0.238
0.893
1.14
769
0.252
0.996
1.1
798
0.232
0.94
1
729
904
0.239
0.167
0.908
0.75
1
0.67
999
0.159
0.67
0.53
46
0.459
0.435
0.21
0.19
Conventional Scaling
• Ends in your lifetime
• …perhaps in your first few years out of
school…
• Perhaps already:
– "Basically, this is the end of scaling.”
• May 2005, Bernard Meyerson, V.P. and chief
technologist for IBM's systems and technology
group
47
Penn ESE370 Fall 2010 -- DeHon
Admin
• ARM Talk Tomorrow (Thursday)
– Raisler 1:30pm – 3:00pm
• HW4 due Friday
48
Penn ESE370 Fall 2010 -- DeHon
Big Ideas
[MSB Ideas]
• Moderately predictable VLSI Scaling
– unprecedented capacities/capability growth
for engineered systems
– change
– be prepared to exploit
– account for in comparing across time
– …but not for much longer
49
Penn ESE370 Fall 2010 -- DeHon