Chapter 5 Combination Logic
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5-1 Basic Combinational Logic Circuits
5-2 Implementing Combinational Logic
5-3 Design Procedure
5-4 Characters of Nand and Nor
5-5 Nand and Nor Implementation
5-6 Troubleshooting
5-7 Programmable Logic Devices
5-8 Digital System Application
Logic circuits
Digital Logic
Combinational circuits
Sequential circuits
5-1 Basic Combinational
Logic Circuits
x1
x2
xn
Combinational
circuits
Z1
Z2
Zn
Z1＝f1 (x1，x2, …xn)
Z2＝f2 (x1，x2, …xn)
Zn＝fn (x1，x2, …xn)
5-2 Implementing
Combinational Logic
The first step in the analysis is to make sure
that the given circuit is combinational and not
sequential.
The diagram of a combinational circuit has logic
gates with no feedback path or memory
elements.
A
B
≥1
1
A＋B
A
≥1
≥1
F
A ＋B
1 B
F  A  B  A  B  ( A  B)( A  B)  AB  AB
5-2 Implementing
Combinational Logic
•Truth Table
The truth table can be derived from the
Boolean function and logic diagram.
Once we have the truth table for the circuit, we
can also directly write a logic expression-the
canonical sum or product-if we wish.
5-3 Design Procedure
The Design procedure involves the following steps:
1.From the specification of the circuit,determine
the required number of inputs and outputs and
assign a symbol to each.
2. Derive the truth table that defines the required
relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for
each output as a function of the input variables.
4. Draw the logic diagram and verify the
correctness of the design.
5-3 Design Procedure
Example: Use NAND gates to realize the follow function
F ( A, B, C , D)  m(4,5,6,7,8,9,10,11,12,13,14)
Example: Use NAND gates to realize the follow function
F ( A, B, C , D)  m(4,5,6,7,8,9,10,11,12,13,14)
Conclusion:
CD
AB
00
01
11
10
00
1
1
1
01
1
1
1
11
1
10
1
1
1
1
F  A B  AB  BC  A D
F  AB  AB  BC  AD
A
B
A
1
1
&
&
B
 AB  AB  BC  AD C
 AB  AB  BC  AD
&
&
1
&
D
1
F
F  A B  AB  BC  A D
 A( B  D)  B ( A  C )
 A BD  B AC
 A BD  B AC
A
&
&
D
&
&
C
&
B
F
We can get another NAND-NAND express
F  A B  AB  BC  A D
 A B  AB  BC  A D  B D  AC
 A( B  C  D )  B ( A  C  D)
 A BCD  B ACD
 A ABCD  B ABCD
Only use 4 NAND gates
Since
ABCD  A( A  BCD)  A ABCD
B ACD  B( B  ACD)  B ABCD
5-4 Characters of Nand and Nor
Two-Level Implementation
The procedure for implementing a Boolean function
with two levels of NAND gates is as follows:
1. Simplify the function and express it in sum of
products.
2. Draw a NAND gate for each product term of the
expression that has at least two literals.
5-4 Characters of Nand and Nor
The procedure for implementing a Boolean function
with two levels of NAND gates is as follows:
3. Draw a single gate using the AND-invert or the
invert-OR graphic symbol in the second level,
with the inputs coming from outputs of first level
gates.
4. A term with a single literal requires an inverter in
the first level. It can also be connected directly to
an input of the second level NAND gate.
5-5 Characters of Nand and Nor
NAND Circuits
The Realtionship between AND,OR and NAND
gates.
5-5 Nand and Nor Implementation
Two equivalent graphic symbols for the NAND
gate are shown below,
Logically equivalent
F= (xyz)
F= x +y + z =(xyz)
5-5 Nand and Nor Implementation
Example:
implement the following Boolean function with
NAND gates:
F  ( A, B, C , D)  m(14,13,12,11,9,7,6,5,1)
CD
AB
00
01
10
1
00
01
11
1
1
11
1
10
1
1
1
1
1
F   C D  ABC  AB D  ABD
 C D  ABC  AB D  AB C  BC D  ABD
 DCD  BC AD  AB CD  ABD
 DCD  BC ABD  AB CD  AD ABD
 DCD  BC ABD  AB CD  AD ABD
5-5 Nand and Nor Implementation
Multilevel NAND Circuits
The procedure for converting a multilevel AND-OR
diagram into an all-NAND diagram using mixed
notation as follows:
1. Convert all AND gates to NAND gates with ANDinverter graphic symbols.
2. Convert all OR gates to NAND gates with inverterOR graphic symbols.
3. For every bubble that is not compensated by
another small circle along the same line, insert an
inverter or complement the input literal.
5-5 Nand and Nor Implementation
Example:
5-5 Nand and Nor Implementation
NOR Implementation
The NOR operation is the dual of the NAND
operation. Therefore, all procedures and rules for
NOR logic are the dual of the corresponding
procedures and rules developed for NAND logic.
5-5 Nand and Nor Implementation
Wired logic
F= (AB) (CD)=(AB+CD)
F= (A+B) +(C+D)
=[ ( A+B) (C+D) ]
5-6 Troubleshooting
BIN/OCT
A0
A1
A2
STA
STB
STC
1
2
4
& EN
0
1
2
3
4
5
6
7
C
PQ
Y0
Y1
Y2 1
Y3 Q
Y4
Y5 2
Y6 Q
Y7 3
Q
4
Z
5-7 Programmable Logic Devices
VDD
CP
＋
vI
－
＋
TG
C
CP
R
vO
－
5-8 Digital System Application
5-8 Digital System Application