ECE 511: Digital
System &
Microprocessor
Course Outline
Week
Subject
W1-W2
Digital Logic Review
W2-W3
Microprocessor Architecture & Overview
W3-W6
Microprocessor Instruction Set & Programming
W6-W9
Memory Interfacing
W10-W14
Parallel I/O Interfacing
References




J. L. Antonakos, “The 68000 Microprocessor: Hardware
and Software Principles & Applications,” 5th Ed., Pearson
Prentice-Hall, 2004.
C. M. Gilmore, “Microprocessors: Principles &
Applications,” 2nd Ed., McGraw-Hill, 1995.
A. Clements, “Microprocessor System Design,” PWSKent, 1992.
J. Palmer & D. Perlman, “Introduction to Digital
Systems,” Schaum’s Outlines Series, McGraw-Hill, 1993.
Course Evaluation
Tests x 2
 Quizzes x 3
 Mini Projects

30%
20%
50%
If you have problems, please
contact me:
Ahmad Ihsan bin Mohd Yassin
Rm. T2-A13-1A, Dept. of Comp. Eng.
Faculty of Elect. Eng.
UiTM, Shah Alam.
03-55436118, 017-2576295
*Please call before you see me.
Digital Logic
Review: Part I
ECE 511: Digital System &
Microprocessor.
What we will learn in this session:
Review of logic gates.
 Flip-flops.
 Universal representation of logic gates.
 Decoders.

Gates
What are gates?

Gates are:
 Simple electronic devices.
 Constructed using transistors.
 Used to design digital systems.

Three basic gates:
 AND
 OR
 NOT

Usually packed into ICs.
Gates as Building Blocks
Basic Gate - AND

The AND gate is similar to multiply operation.
A
AND
C
B
A B  C
A B  C
TRUTH TABLE
A
B
C
0
0
0
1
0
0
0
1
0
1
1
1
Basic Gate - OR

The OR gate is similar to add operation.
A
OR
C
B
A B  C
A B  C
TRUTH TABLE
A
B
C
0
0
0
1
0
1
0
1
1
1
1
1
Basic Gate - NOT

The NOT gate performs the inverse operation.
A
A  B
NOT
B
A B
TRUTH TABLE
A
B
0
1
1
0
Extended Gates

Combination of basic gates to perform
complex functions:
 NAND
 NOR
 XOR
 XNOR
 Flip-Flops
NAND Gate


Adds NOT after AND gate.
AND outputs are inverted  NAND (NOT-AND).
A
A
AND
B
NOT
C
NAND
C
B
A B  C
TRUTH TABLE
A
B
C
0
0
1
1
0
1
0
1
1
1
1
0
NOR Gate


Adds NOT after OR gate.
OR outputs are inverted  NOR (NOT-OR).
A
A
OR
B
NOT
C
NOR
C
B
A B  C
TRUTH TABLE
A
B
C
0
0
1
1
0
0
0
1
0
1
1
0
)
XOR Gate


XOR performs the Exclusive Or operation.
When A=B, C=0; when A≠B, C=1.
A
B
A B  C
)
XOR
C
AB  AB  C
TRUTH TABLE
A
B
C
0
0
0
1
0
1
0
1
1
1
1
0
)
XNOR Gate


A
B
Adds NOT after XOR gate.
XOR outputs inverted  XNOR (NOT XOR).
)
A
XOR
NOT
C
B
)
XOR
C
A  B A  B  C
TRUTH TABLE
A
B
C
0
0
1
1
0
0
0
1
0
1
1
1
Flip-Flops
Flip-Flops




Extended gate.
2 gates, feedback connections.
2 inputs, 4 states.
Used as memory:
 Each FF stores 1 bit.
 Unchanged at “keep”

state.
More complex ones may:
 Use
timing from CLK.
 Perform bit toggle.
RS Flip-Flop

4 states:
 Three
stable.
 One not stable.


2 inputs, 2 outputs.
May contain clock (CLK) signal.
RSFF - NOR Implementation
S
Q’
*Assuming initial condition:
S = 0, R = 0, Q = 0
R
Q
*As long as S=0 and R=0,
Q will always remain at previous state.
Qprev
S
R
Q
Q’
Output unchanged
N/A
0
0
0
1
Output set (Q = 1)
0
1
0
1
0
Output reset (Q = 0)
1
0
1
0
1
Doesn’t
matter
1
1 N/A N/A
Unstable
RS Flip-Flop (NAND Implementation)
S
Q
R
*Assuming initial condition:
S = 0, R = 0, Q = 0
Qprev
S
R
Q
Q’
N/A
0
0
0
1
Output set (Q = 1)
0
1
0
1
0
Output reset (Q = 0)
1
0
1
0
1
Doesn’t
matter
1
1 N/A N/A
Q’
Output unchanged
*As long as S=0 and R=0,
Q will always remain at Qprev.
Unstable
Clocked RS
S
Q’
CLK
Q
R
Only active when CLK
is ↑
Qprev
S
R CLK Q
Q’
Output unchanged
N/A
0
0
↑
0
1
Output set (Q = 1)
0
1
0
↑
1
0
Output reset (Q = 0)
1
0
1
↑
0
1
Doesn’t
matter
1
1
Doesn’t
matter
Reduced sensitivity to noise.
Unstable
N/A N/A
JK Flip-Flop
Same as RS, but forbidden state used to
toggle bit.
 Can also be clocked using CLK.

Qprev
S
R
Q
Q’
Output unchanged
N/A
0
0
0
1
Output set (Q = 1)
0
1
0
1
0
Output reset (Q = 0)
1
0
1
0
1
Q
1
1
Q
Q
Toggle
JK Flip-Flop (Palmer & Perlman, pg. 200)
J
Q
K
Q
Qprev
S
R
Q
Q’
Output unchanged
N/A
0
0
0
1
Output set (Q = 1)
0
1
0
1
0
Output reset (Q = 0)
1
0
1
0
1
Q
1
1
Q
Q
Toggle
Clocked JK (Palmer & Perlman, pg. 200)
J
Q
CLK
K
Q
Qprev
S
R CLK Q
Output unchanged
N/A
0
0
↑
0
Output set (Q = 1)
0
1
0
↑
1
Output reset (Q = 0)
1
0
1
↑
0
Q
1
1
↑
Q
Toggle
D-Flip-Flop
Data latch.
 Modification of RSFF.
 Stores 1-bit of information.

 Can

be combined to store more.
How data stored in memory.
D-Flip-Flop
D
Q’
EN
Q
Qprev
Only active when EN
is 1
D EN Q
Q’
Output set (Q = 1)
Doesn’t Matter
1
1
1
0
Output reset (Q = 0)
Doesn’t Matter
0
1
0
1
D-Flip-Flop: Timing Diagram
D
EN
Q
Storing 8-bits using DFF
D0
D1
D2
D3
D4
D5
D6
D7
DFF
DFF
DFF
DFF
DFF
DFF
DFF
DFF
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
EN
Asynchronous Latch

Allows both synchronous & asynchronous
operations:
 Synchronous:
CLK driven (Clocked JK).
 Asynchronous: similar to RSFF.

5 inputs, 2 outputs:
 J,
K and CLK for synch. operation.
 PR, CLR for asynch. operation.
Asynchronous Latch (Perlman, pg. 201)
PRE
J
Q
CLK
K
PRE
1
1
0
0
CLR
1
0
1
0
Q
Follows J, K, CLK (Synch. JK)
Q = 0, resets output.
Q = 1, sets output.
Not valid.
Q
PRE
CLR
PRE
0
0
1
1
CLR
0
1
0
1
J
Q
Follows J, K, CLK (Synch. JK)
Q = 0, resets output.
Q = 1, sets output.
Not valid.
Q
CLK
K
Q
CLR
Universal Gates –
NAND and NOR
NAND and NOR as Universal
Gates
In industry, NAND and NOR gates are
most common.
 Reason?

 Can
be used to represent any gate
(functionally complete).
 Easiest & cheapest to produce.
NAND Logic
NAND
NOT
AND
NAND
NAND
NOR Logic
NOR
NOT
NOR
AND
NOR
NOR
NAND Logic
NAND
OR
NAND
NAND
NAND
NAND
NAND
XOR
NAND
NOR Logic
OR
NOR
NOR
NOR
NOR
NOR
XOR
NOR
NOR
IC 4011
IC 7402
Decoders
Decoders

Electronic device that:
 Reverse
of an encoder.
 “Translates” binary codes back into signal.
 Converts n inputs into 2n combinations.

Uses:
 Activate
devices for use by µP.
 Memory, I/O interfacing.
Encoder vs. Decoder
8  3 Encoder
I0
I1
I2
I3
I4
I5
I6
I7
I0
1
0
0
0
0
0
0
0
I1
0
1
0
0
0
0
0
0
Y2
Y1
Y0
I2
0
0
1
0
0
0
0
0
I3
0
0
0
1
0
0
0
0
I4
0
0
0
0
1
0
0
0
I5
0
0
0
0
0
1
0
0
I6
0
0
0
0
0
0
1
0
I7
0
0
0
0
0
0
0
1
Y0
0
0
0
0
1
1
1
1
Y1
0
0
1
1
0
0
1
1
Y2
0
1
0
1
0
1
0
1
Encoder vs. Decoder
3  8 Decoder
I0
I1
I2
I3
I4
I5
I6
I7
Y2
Y1
Y0
Y2
0
0
0
0
1
1
1
1
Y1
0
0
1
1
0
0
1
1
Y0
0
1
0
1
0
1
0
1
I7
0
0
0
0
0
0
0
1
I6
0
0
0
0
0
0
1
0
I5
0
0
0
0
0
1
0
0
I4
0
0
0
0
1
0
0
0
I3
0
0
0
1
0
0
0
0
I2
0
0
1
0
0
0
0
0
I1
0
1
0
0
0
0
0
0
I0
1
0
0
0
0
0
0
0
What Goes on Inside a Decoder?
Y0
Y1
I0 = Y0Y1Y2
I1 = Y0Y1Y2
I2 = Y0Y1Y2
Y2
I3 = Y0Y1Y2
I4 = Y0Y1Y2
I5 = Y0Y1Y2
I6 = Y0Y1Y2
I7 = Y0Y1Y2
Code
000
001
010
011
100
101
110
Device
LED
DC Motor
Memory #1
Memory #2
Memory #3
Memory #4
LCD Display
Device Code
Decoder
Activate Signal
Decoders in Action
74LS139 Dual 2-4 Line Decoder
Motorola 2-4 decoder.
 2 x decoders in one IC.
 16 pins total:

2
inputs, 4 outputs (active low).
 Vcc (±5V) and GND.
 2 x Enable pins.
74LS139 Dual 2-4 Line Decoder
O0a
Ea
A0a
A1a
O1a
O2a
O3a
O0b
Eb
A0b
O1b
A1b
O2b
O3b
74LS139 Truth Table
E
I1
I0
O3
O2
O1
O0
1
X
X
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
74LS138 3-8 Line Decoder
Motorola 3-8 decoder.
 1 x decoder in one IC.
 16 pins total:

3
inputs, 8 outputs (active low).
 Vcc (±5V) and GND.
 3 x Enable pins.
74LS138 3-8 Line Decoder
E1
O0
E2
O1
E3
O2
O3
A0
A1
O4
O5
O6
A2
O7
74LS138 Truth Table
E1 E2 E3 I2
I1
I0
O7 O6 O 5 O4 O3 O2 O1 O0
1
X X
X X X
1
1
1
1
1
1
1
1
X
1
X
X X X
1
1
1
1
1
1
1
1
X X
0
X X X
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
Conclusion

Gates: most basic elements in circuits.
 Can
be extended to perform advanced
functions.
 Some types are universal.
 Flip-flops can store data – feedback.

Decoders transform code into original
signals.
 Can
be used to control access to hardware.
The End
Please read:
Palmer & Perlman, pg.194-203.
http://computerscience.jbpub.com/ecoa/2e/Null03.pdf