Operating Systems
Lecture 34
Paging Implementation
Operating System Concepts
7.1
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Implementation of Page Table
Recall:
 Simplest implementation: Page table stored in
dedicated registers in the CPU.
 The registers use high speed logic.
 The CPU dispatcher re-loads these registers when
switching processes. (Each process has its own page
table).
 This method is only useful when the page table is small
(< 256 entries).
 Most contemporary computers have much larger page
tables (106 entries) so this method will not work well.
Operating System Concepts
7.2
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Storing Page Table in Main Memory
 For large page tables, the page table is kept in main




memory.
Page-table base register (PTBR) points to the page
table.
When changing processes, only need to change 1
register to change page tables. This reduces the
context switch time.
Page-table length register (PTLR) indicates size of the
page table.
Drawback: In this scheme every data/instruction
access requires two memory accesses. One for the
page table and one for the data/instruction.
Operating System Concepts
7.3
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Translation Look-Aside Buffer (TLB)
 The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers
(TLBs)
 This kind of memory is expensive, so it is generally
small (64 - 1024 entries).
 In each memory access, the TLB is searched first to
locate the page number.
 If the page is found (a hit) the associated frame is
used to access the data in memory.
 If the page is not found (a miss), the page number
is looked up in the page table in main memory. The
page number and associated frame is added to the
TLB.
Operating System Concepts
7.4
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
TLB: Associative Memory
 Associative memory – parallel search
Page #
Frame #
Address translation (Page #, Frame #)
 If page# is in associative register, get frame # out.
 Otherwise get frame # from page table in memory
Operating System Concepts
7.5
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Paging Hardware With TLB
Operating System Concepts
7.6
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Effective Access Time (EAT)
 Effective access time (EAT) is the average time needed to
access memory.
 Hit Ratio: The percentage of times that a particular page
number is found in the TLB.
 Effective access time can be calculated based on:
 The time it takes to access main memory
 The time it takes to access the TLB
 The hit ratio for the TLB
 Example
 Time to access main memory = 100ns
 Time to access TLB = 20 ns
 Hit ratio = 0.8 (80%)
 If page is found in TLB, total access time = ?
 If page is not found in TLB, total access time = ?
 Effective access time = ?
Operating System Concepts
7.7
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
General Formula for EAT
 Hit ratio = a
 Main Memory access time = m
 Associative Lookup (TLB access) = e
 EAT = (m + e) a + (2m + e) (1 - a)
= 2m - ma + e
Operating System Concepts
7.8
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Memory Protection
 Memory protection implemented by associating protection bit with each
frame.
 Bits signal if a frame is read only, read-write, execute only or a combination.
 Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the process’ logical address
space, and is thus a legal page.
 “invalid” indicates that the page is not in the process’ logical address space.
 Example:
 System has 14 bit address space (0 - 16383)
 Program uses addresses 0 - 10468
 Page size = 2 KB (2048 = 211)
 # of pages = ?
 6 pages needed by program (5 pages = 5*2048 = 10240Bytes)
 Pages 0 - 5 have valid/invalid bit set to valid
 Other pages have bit set to invalid.
Operating System Concepts
7.9
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Valid (v) or Invalid (i) Bit In A Page Table
Operating System Concepts
7.10
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Problem with large page tables
 Modern computers have large logical address spaces:
232 or 264 bytes.
 This can make page tables excessively large.
 Example: 32 bit logical address space
4 KB Page size
 How many entries in the page table?
 If each entry is 4 bytes, what is size of each table?
 With large page tables, it is good not to store them
continuously in memory.
Operating System Concepts
7.11
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Hierarchical Page Tables
 In hierarchichal page tables, the logical address space is broken up
into multiple page tables.
 A two-level example: A logical address (on 32-bit machine with 4K
page size) is divided into:
 a page number consisting of 20 bits.
 a page offset consisting of 12 bits.
 Since the page table is paged, the page number is further divided into:
 a 10-bit page number.
 a 10-bit page offset.
 Thus, a logical address is as follows:
where p1 is an index into the outer page table, and p2 is the
displacement within the page of the outer page table.
page number
pi
10
Operating System Concepts
page offset
p2
d
10
12
7.12
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Address-Translation Scheme
 Address-translation scheme for a two-level 32-bit paging
architecture
Operating System Concepts
7.13
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Two-Level Page-Table Scheme
Operating System Concepts
7.14
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Hashed Page Tables
 Common in address spaces > 32 bits.
 The virtual (logical) page number is hashed into a page
table. This page table contains a chain of elements
hashing to the same location.
 Virtual page numbers are compared in this chain
searching for a match. If a match is found, the
corresponding physical frame is extracted.
Operating System Concepts
7.15
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Hashed Page Table
Operating System Concepts
7.16
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Inverted Page Table
 One entry for each real page (frame) of memory.
 Entry consists of the virtual address of the page stored in
that real memory location, with information about the
process that owns that page.
 Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs.
Operating System Concepts
7.17
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Inverted Page Table Architecture
Operating System Concepts
7.18
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Shared Pages
 Shared code
 One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
 Shared code must appear in same location in the logical
address space of all processes.
 Private code and data
 Each process keeps a separate copy of the code and
data.
 The pages for the private code and data can appear
anywhere in the logical address space.
Operating System Concepts
7.19
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005
Shared Pages Example
Operating System Concepts
7.20
Silberschatz, Galvin and Gagne 2002
Modified for CSCI 399, Royden, 2005