Threshold Logic for Nanotechnologies
1
Zvi Kohavi and Niraj K. Jha
Introductory Concepts
Threshold element or gate:
x1
w1
x2
w2
T
y
wn
xn
Example: y = f(x1,x2,x3) = (1,2,3,6,7) = x1’x3 + x2
x1
-1
x2
1_
2
2
y
1
x3
2
MOBILEs
Monostable-bistable transition logic element (MOBILE): a resonant
tunneling diode (RTD) and heterostructure field-effect transistor
(HFET) nanotechnology based threshold element
• Rising edge-triggered, current-controlled gate
• Serially-connected load and driver RTDs
• RTD-HFET structures in parallel to the load (driver) RTDs perform positive
(negative) weighting of inputs
• Area of RTDs: corresponds to weight
• Difference in the areas of the driver and load RTDs: threshold
Clk
RTD
Positiveweight inputs
Load
w1
x1
w2
x2
f
HFET
-w3
T
x3
Driver
Negativeweight input
3
Majority Gates
Majority gate: a special type of threshold element
• A three-input majority gate: produces a 1 if a majority of its inputs are 1
M(x1,x2,x3) = x1x2 + x2x3 + x1x3
• Can be implemented as a threshold element: with w1 = w2 = w3 = 1 and
T=2
• Acts like an AND (OR) gate when one of its inputs is tied to 0 (1)
Nanotechnology implementations: quantum cellular automata (QCA),
single-electron box (SEB)
Input x1
0
Input x2
1
1
Input x3
Device
cell
Output
cell
Node 1
Inputs
x1
x2
x3
C
C
C
Vd
CL
CL
C0
Cj
Cj
Node 2 Output
terminal
C
f3
C
f2
C f
1
Output
capacitor
Input
capacitor
1
QCA
SEB
4
Minority Gates
Minority gate: produces a 1 if a majority of its inputs are 0
m(x1,x2,x3) = x1’x2’ + x2’x3’ + x1’x3’
• Acts like a NAND (NOR) gate when one of its inputs is tied to 0 (1)
Nanotechnology implementation: tunneling phase logic (TPL)
Clock 1
Ci
J1
J2
Clock 2
Cj
J4
Pump
J3
Pump
TPL
5
Capabilities and Limitations of Threshold
Logic
Threshold gate: generalization of conventional gates
• More powerful than conventional gates because it can realize a larger
class of functions
• Any conventional gate can be realized with a threshold gate
• Thus, threshold gates are functionally complete
Example: NAND implementation
x1
-1
-11_
2
y
-1
x2
6
Is Every Switching Function Realizable by
One Threshold Element?
Answer: No
Example: Let f(x1,x2,x3,x4) = x1x2 + x3x4
• Output value must be 1: for x1x2x3’x4’, x1’x2’x3x4
• Output value must be 0: for x1’x2x3’x4, x1x2’x3x4’
• Since the requirements in the inequalities are conflicting, no threshold
value can satisfy them
– Thus, the function is not realizable by a single threshold element
7
Basic Problem of Threshold Logic
Given a switching function f(x1,x2, …,xn): determine whether it is realizable
by a single threshold element, and if it is, find appropriate
weights and threshold
• Such a function is called a threshold function
Straightforward approach: Solve a set of 2n linear, simultaneous
inequalities
Example: Let f(x1,x2,x3) = (0,1,3)
Combination 0: T must be negative
Combinations 2, 4: w2, w1 must be
negative
Combinations 3, 5: w2 must be
greater than w1
Combination 1: w3 is greater than
or equal to T
Thus, w3 T > w2 > w1
w1 = -2, w2 = -1, w3 = 1, T = -1/2
8
Sensitivity to Variations
Limitation: Due to variations in input and supply voltages, the weighted
sum may deviate from its prescribed value and cause circuit
malfunction
• Restrictions imposed on the number of inputs and threshold T
• Introduce defect tolerances: non-negative
and
9
Elementary Properties
Weight-threshold vector: V = {w1,w2, …,wn;T}
Let f(x1,x2, …,xn) be realized by V1 = {w1,w2, …,wj, …,wn;T}. If xj is
complemented, it can be realized by V2 = {w1,w2, …,-wj, …,wn;T-wj} with
inputs x1,x2, …,xj’, …,xn
From V1:
When V2 replaces V1 and xj’ replaces xj: where g is realized by V2
g and f are identical: since the equations reduce to each other for both
xj = 0 and xj = 1
10
Important Conclusions
If a function is realizable using a single threshold element, then by an
appropriate choice of complemented and uncomplemented input
variables: a realization with any sign distribution is possible
Corollary: if a function is realizable by a single threshold element, then it is
realizable by an element with only positive weights
11
Important Property
If f(x1,x2, …,xn) is realizable by a single threshold element with V1 = {w1,w2,
…,wn;T}, then its complement is realizable by a single threshold element
with V2 = {-w1,-w2, …,-wn;-T}
From V1:
Multiplying both sides by -1:
Thus, f’ is realizable by V2
12
Synthesis of Threshold Networks
Unate functions: function f(x1,x2, …,xn) is positive (negative) in variable xi if
there exists a disjunctive or conjunctive expression for the
function in which xi only appears in uncomplemented
(complemented) form
If f is either positive or negative in xj: it is said to be unate in xi
Example: f = x1x2’ + x2x3’ is positive in x1 and negative in x3, but not unate
in x2
If f(x1,x2, …,xn) is unate in each of its variables: then it is called unate
Example: f = x1’x2 + x1x2x3’ is unate since it can be simplified to x1’x2 + x2x3’
Example: f = x1x2’ + x1’x2 is not unate in either variable
13
Unate Functions
If f(x1,x2, …,xn) is positive in xi: then it can be expressed as
and vice versa
If f(x1,x2, …,xn) is negative in xi: then it can be expressed as
and vice versa
14
Geometric Representation
n-cube: contains 2n vertices, each of which represents an assignment of
values to n variables and thus corresponds to a minterm
• a line is drawn between every pair of vertices which differ in just one
variable
• Vertices for which the function is 1 (0) called: true (false) vertices
Example: Three-cube representation for f = x’y’ + xz
(1,1,1)
(1,1,0)
(0,1,1)
(1,0,1)
(0,1,0)
(1,0,0)
(0,0,1)
(0,0,0)
15
Partial Ordering
Partial-ordering relation between vertices of the n-cube:
(a1,a2, …,an)  (b1,b2, …,bn)
if and only if for all i, ai  bi
•
•
•
•
Partially ordered set of vertices: a lattice
(0,0, …,0): least vertex
(1,1, …,1): greatest vertex
Some pair of variables incomparable: e.g., (0,0, …,0,1) and (1,0, …,0,0)
Without loss of generality: concentrate on positive unate functions
Example: relabel x1’x2x3’ + x2x3’x4 as x1x2x3 + x2x3x4
• By reconverting the latter: possible to determine the original function
16
Unate Function Theorem
Theorem 1: f(x1,x2, …,xn) is unate if and only if it is not a tautology and the
above partial ordering exists, such that for every pair of vertices,
(a1,a2, …,an) and (b1,b2, …,bn), if (a1,a2, …,an) is a true vertex and
(b1,b2, …,bn)  (a1,a2, …,an), then (b1,b2, …,bn) is also a true vertex of f
Minimal true vertex: A true vertex Si is said to be minimal if no other true
vertex Sj < Si
Maximal false vertex: A false vertex Si is said to be maximal if no other
false vertex Sj > Si
Example: For x1x2 + x3x4
• Minimal true vertices: S1 = (1,1,0,0), S2 = (0,0,1,1)
• Thus, every vertex greater than S1 or S2 must be a true vertex: e.g.,
(1,1,1,0), (0,1,1,1)
– These vertices correspond to x1x2x3 and x2x3x4, which are covered by
f
17
Linear Separability
For an n-cube representation for threshold functions: linear equation
w1x1 + w2x2 + … + wnxn = T
corresponds to an (n-1)-dimensional hyperplane that cuts through the
n-cube
• Since f = 0 when
w1x1 + w2x2 + … + wnxn < T
• and f = 1 when
w1x1 + w2x2 + … + wnxn  T
the hyperplane separates the true vertices from the false ones
Such a function is called a linearly separable function
• Thus, every threshold function is linearly separable, and vice versa
18
Theorems
Theorem 2: Every threshold function is unate
Theorem 3: Given an expression for a unate switching function,
f(x1,x2, …,xn), replace xj by xk’, resulting in f(x1,x2, …,xn). If g is not a
threshold function, then neither is f
Example: Let f = x1x2 + x3x4
•
•
•
•
To determine if f is a threshold function: replace x2 by x3’
This results in g = x1x3’ + x3x4
Since g is not unate in x3, it is not a threshold function
Hence, neither is f
19
Identification and Realization of Threshold
Functions
Procedure:
1.
2.
3.
4.
Test the given function f for unateness
If it is unate, convert it into another function g that is positive in all its variables
Find all minimal true and maximal false vertices of g
Derive and solve a system of pq inequalities, corresponding to the p minimal
true and q maximal false vertices
- For minimal true vertex A = {a1,a2, …,an} and maximal false vertex
B = {b1,b2, …,bn}, write
w1a1 + w2a2 + … + wnan > w1b1 + w2b2 + … + wnbn
20
Identification Example
Example: Given f = x1x2x3’x4 + x2x3’x4’
1. Reduce to f = x1x2x3’ + x2x3’x4’, which is unate
2. g = x1x2x3 + x2x3x4
3. Minimal true vertices: (1,1,1,0), (0,1,1,1);
Maximal false vertices: (1,1,0,1), (1,0,1,1), (0,1,1,0)
4. p = 2 and q = 3 yields 6 inequalities:
5. Necessary constraints that must be satisfied: V = {1,2,2,1; 9/2} for g
=> V = {1,2,-2,-1; 3/2} for f
21
Map-based Synthesis of Two-level
Threshold Networks
Decomposition of non-threshold functions: into two or more factors that are
threshold functions
Admissible pattern: a pattern of 1 cells that can be realized by a single
threshold element
• An admissible pattern may be in any position on the map
• An admissible pattern for functions of three variables is also an admissible
pattern for functions of four or more variables
• Since the complement of a threshold function is also a threshold function,
patterns of 0 cells are also admissible
• Select a minimal number of admissible patterns such that each 1 cell is
covered by at least one admissible pattern
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
22
1
Synthesis Example
Example: For f(x1,x2,x3,x4) = (2,3,6,7,10,12,14,15), find a minimal
threshold-logic realization
x1 x2
x3 x4
00
01
11
10
1
00
01
11
1
1
1
10
1
1
1
1
g
h
(a) Map for f exhibiting two admissible patterns
x1
x1
x2
x2
-2
1
3
1
x3
5
2
2
1
1
-1
g
x3
x4
5
2
h
x4
(b) Threshold elements realizing the admissible patterns
x1
x1
x2
-2
1
3
1
x3
x4
x2
5
2
2
1
3
1
-1
g
x3
x4
(c) Threshold-logic realization of f
5
2
f
23
Another Synthesis Example
Example: For f(x1,x2,x3,x4) = (3,5,7,10,12,14,15), find a minimal
threshold-logic realization
x1 x2
x3 x4
00
01
x1
x3
x4
10
x1
x2
x4
1
00
01
11
11
1
1
1
1
1
10
x2
x3
x4
x1
x2
x4
x1
x3
x4
1
(b) AND-OR realization of f
(a) Map showing a minimal set of prime
implicants which cover f.
x1 x2
x3 x4
00
01
01
10
10
1
00
11
11
1
x2
1
1
x1
x1
1
1
f
-1
1
1
2
x3
1
x4
x2
1
2
2
2
1
1
32
1
-1
g
x3
2
1
2
f
x4
(d) A threshold-logic realization of f
24
(c) Map showing the admissible pattern
realized by each threshold element.
Synthesis of Multi-level Threshold
Networks
Example: One-to-one map from the following network to a threshold
network requires seven threshold elements (including the
inverter) and five logic levels – quite sub-optimal
• Reason: some nodes can be collapsed into a single threshold node
x1
x2
x3
n4
n5
x1
x4
n3
x5
n1
f
x6
x7
n2
(a) Switching network
Assuming a fanin restriction of four:
•
•
•
•
Collapse f = n1 + n2 to n3x5 + x6x7
Since f is not threshold: split it into n1 + x6x7, where n1 = n3x5
Since n1 + x6x7 is threshold: synthesize n1 next
x1
Since n1 = n4x5 + n5x5 is threshold:
x5
1
n
4
x2
1
3
synthesize n4 = x1x2x3 and
2
1
1 3
x3
1
n5
n5 = x1’x4, which are both threshold
x
1
x6
n1
1
2
2
1
f
x7
-1 1
1
x4
25
(b) Equivalent threshold network
General Synthesis Procedure
Procedure:
1. Start with a multi-output algebraically-factored switching network G
2. Process each primary output of G
• If the node represents a binate function, split into multiple nodes and
process recursively
• If the node is unate and is also a threshold function, save it in the
threshold network and process its input nodes recursively
• Else, split the unate node into two or more nodes that are
threshold functions
3. Terminate procedure when all the nodes in G are mapped to threshold
nodes
26
Mapping Threshold Networks to MOBILEs
MOBILE: a self-latching threshold gate because its output is valid only
when the clock is high
Four-phase clocking: all signals to any threshold element must arrive in the
same clock phase
• Ensured by inserting buffers as necessary
27
MOBILE Example
Full-adder:
Level:
2
1
3
a
1
1
1
b
c0
2
ci
-2
1
1
1
CLK
1
s
wa=1
threshold
buffer
a
a
f
(a) Network before inserting buffers
1
1
2
1
T=2
Level:
2
1
3
a
b
1
1
1
c0
2
ci
-2
1
1
1
1
s
threshold
buffer
(b) Network after inserting buffers
28
f
Synthesis of Multi-level Majority/Minority
Networks
Realizable pattern: pattern of 1 cells realizable by a majority gate
• For three-input positive functions: 10 realizable patterns
• Removing the restriction that function be positive: 38 realizable patterns
x1x2
00
x3
01
11
10
0
1
1
1
1
1
x1x2
00
x3
11
0
1
1
0
1
1
1
1
x1 = M(x1, 1, 0) = M(x1, 0, 1)
x1x2
00
x3
0
1
1
01
11
1
1
1
1
10
x2 = M(1, x2, 0) = M(0, x2,1)
x1x2
00
x3
10
1
0
1
1
1
0
1
1
1
1
1
11
10
x1x2
00
x3
1
0
1
1
1
x1x2= M(x1, x2, 0)
01
11
10
0
1
x1x2
00
x3
10
01
1
x2x3= M(0, x2, x3)
10
1
1
1
01
1
1
11
10
1
1
1
1
11
10
1
1
x1x3= M(x1, 0, x3)
x1x2
x3
00
01
0
1
11
x1 + x3 = M(x1, 1, x3)
x1 + x2 = M(x1, x2, 1)
01
01
x3 = M(1, 0, x3) = M(0, 1, x3)
11
0
x1x2
00
x3
1
01
x2 + x3 = M(1, x2, x3)
x1x2
00
x3
x1x2
00
x3
01
1
11
10
1
1
1
1
x1x2 + x1x3 +x2x3 = M(x1, x2, x3)
29
Synthesis Example
Example: Consider f = x1’x2’x3’ + x1’x2x3 + x1x2x3’ + x1x2’x3
• Naïve approach: decompose network into two-input AND and OR gates
and replace each such gate by a reduced majority gate
• However, if we make full use of the three inputs of a majority gate: only
four gates necessary
• Minority network: can be obtained from a majority network using De
Morgan’s theorem
x1
x2
x3
x1
x2
x3
x1
x2
x3
x1
x2
x3
f
(a)
x1
x2
x3
M
x1
x2
x3
M
x1
x2
x3
M
f1
f2
M
f3
(b)
f
x1
x2
x3
m
x1
x2
x3
m
x1
x2
x3
m
f1
f2
m
f3
(c)
30
f
General Synthesis Procedure
Procedure:
1. Start with a multi-output algebraically-factored switching network G
2. Decompose G into a network in which nodes have at most three inputs
• If the node represents a majority function, move on to the next node
• If a common literal exists in all the product terms of the node
function, factor it out and perform AND/OR mapping on it
• If a common literal does not exist, check to see if the node can be
implemented with fewer than four AND/OR nodes
• Else, map the node onto at most four majority gates using a
Karnaugh-map based procedure
Example: Consider f = x1x2’+ x2’x3
•
•
With AND/OR mapping, three majority gates are needed:
– f1 = x1x2’, f2 = x2’x3, f = f1 + f2
However, since literal x2’ can be factored out: f = f1x2’ where f1 = x1+x3
– This requires only two majority gates
31
K-map based Procedure
Given the map of a node function n with at most three inputs:
1. Find a realizable pattern f1
2. Find a second realizable pattern f2 based on f1 and n
3. Find the third realizable pattern f3 based on f1, f2 and n
– Realizable patterns chosen such that n = M(f1,f2,f3) = f1f2+f2f3+f1f3
4. f1 may contain makeup minterms that are not minterms of n
– A minterm (maxterm) of n must also be a minterm (maxterm) of at
least two of the three functions, f1, f2 and f3
– Enforce rule by defining two sets:  1 and  0
» For finding f2: if a minterm (maxterm) of n is not a minterm
(maxterm) of f1, add it to  1 ( 0 )
» For finding f3: if a minterm (maxterm) of n is not a minterm
(maxterm) of both f1 and f2: add it to  1 ( 0 )
5. On failure to find f3, backtrack to find new f2
32
Synthesis Example
Example: Consider f = x1’x2’x3’ + x1’x2x3 + x1x2x3’ + x1x2’x3
00
x3
0
01
11
1
1
x3
10
0
1
1
00
0
01
11
01
11
1
1
1
10
x3
00
01
1
Step 2: find f2
00
x3
01
0
0
11
1
Update 1
x1x2
10
00
x3
0
1
1
1
01
Update 0
x1x2
00
x3
0
01
11
10
1
0
(g)
10
1
1
x1
x2
x3
M
x1
x2
x3
M
x1
x2
x3
M
f1
f2
M
f3
(f)
Step 3: find f3
x1x2
00
01
11
10
x3
0
0
11
1
f2 = x1x2+ x2 x3+ x1x3 = M(x1, x2, x3)
(e)
(d)
10
(c)
1
1
1
11
0
1
x1x2
10
Compute1
x1x2
f1 = x1 x2+ x2x3 + x1x3= M(x1, x2, x3)
(b)
Compute 0
x1x2
00
1
1
n = x1x2 x3 + x1 x2x3 + x1 x2x3 + x1 x2x3
(a)
x3
Step 1: find f1
x1x2
x1x2
1
1
1
1
1
f3 = x1x2 + x2 x3+ x1x3 = M(x1, x2, x3)
(h)
33
f