PicoBlaze & MicroBlaze
Ernest Jamro
Dep. Of Electronics
AGH – University of
Science and Technology
MicroBlaze
•32 bit soft-processor
•32 bit instructions
•32 registers
•Independent data and instruction buses
•Different bus standards:
- PLB (Processor Local Bus)
- AXI (Advanced eXtensible Interface)
- LMB (Local Memory Bus)
- FSL (Fast Simplex Link)
2
MicroBlaze Block Diagram
3
Different Bus Configurations
LMB:
AXI / PLB
Complexity
simply
complex
Local/glonal
local
global
# Master
1
>=1
4
MB bus configurations: only LMB
This configuration cannot communicat with external
modules, thus should not be employed
Instr
LMB
MB
Lmb_bram
_if_ctrl
Dane
LMB
Lmb_bram
_if_ctrl
BRAM
(dwu-portowy)
5
LMB: Instructions, PLB:Data
Instr
LMB
MB
LMB_bram
_if_ctrl
Dane
PLB
Peripheral
modules
e.g.. UART,
GPIO,
SRAM
plb_bram
_if_ctrl
BRAM
(dula-port)
6
EDK Print Screen
7
Instructions:LMB; Data: PLB + LMB
MB employs LMB for instructions and memory access
and PLB/AXI for peripheral module access
Instr
LMB
MB
LMB_bram
_if_ctr
Dane PLB
LMB
Peripheral
modules e.g.
UART,
GPIO,
SDRAM
LMB_bram
_if_ctr
BRAM
(dual port)
8
Only one PLB/AXI bus
cache
I
MB
cache
D
Pheripheral
modules e.g.
UART,
GPIO
(external memory)
e.g. plb_ddr
9
Two PLB/AXI buses
Warning: plb_ddr memory cannot be written (how to initialise
instruction memory)
Instr
PLB
cache
I
(Exter. Memory)
e.g. plb_ddr
MB
cache
D
Dane
PLB
Peripheral
Modules
e.g. UART,
GPIO
(Exter. Memory)
e.g. plb_ddr
10
Two PLBs, single memory
Instr
PLB
cache
I
MB
cache
D
Data PLB
Pheripheral
modules
e.g. UART,
GPIO
Multi-channel
Memory controller
FPGA
External
Memory
11
Without Data Cache
Manual (in C program) handling of data memory transfer
Instr
PLB
cache
I
MB
Multi-channel
Memory controller
External
Memory
Dane
PLB
Peripheral
Modules
e.g. UART,
GPIO
lmb_bram_
if_ctrl
BRAM
12
Example (6)
The MB is booted from BRAM
Instr.
PLB
plb_sdram
MB
LMB_bram
_if_ctr
Data PLB
LMB
Peripheral
Modules
e.g. UART,
GPIO
LMB_bram
_if_ctr
BRAM
(dual-port)
13
Fast Simplex Link (FSL)
32-bit single direction bus – one master one slave
14
Registers
•R0-R31 32x32-bit –general purpose registers R0always equal to 0
•PC – Program counter – initial value = 0
•MSR (Machine State Register)
15
MSR
16
Instruction Format
Typu A Instruction
Typu B instruction
Example: instruction ADD
17
Example of Instructions
18
19
Pipeline Architecture
Delay Slot Instructions
20
(Hard)Procesor
(e.g. PowerPC in Virtex 2Pro)
• Implemented directly in silicon (ASIC technology)
• Employs ASIC technology (not FPGA technology) so this
silicon area cannot be reused for other purposes
•Parameters are defined (ASIC) and cannot be changed
•Is relatively fast and consumes relatively small silicon area and
power
21
Soft-procesor (e.g. MicroBlaze)
•Employs standard FPGA logic resources
•thus the logic resources can be freed when not required
•Parameters can be freely defined by a user
•In comparison to the hard-processor is slower, consumes more
silicon area and power
22
MicroBlaze parameters
•Different types of buses (PLB/AXI, LMB)
•(Implement or not) cache memory, define its size
•Barrel-Shifter
•fast multiplier: define the bit-width of the multiplier: 32-bit, 64bit
•divider
•debugger (and its parameters)
•Floating-point unit (and its parameters)
•MMU – Memory Management Unit
23
EDK - Ports
24
EDK Addresses
25
Adding IP-Cores
26
IP-Core Options
27
Microprocessor Hardware Specification
28
8-bit soft-processor PicoBlaze
• Optimized for Xilinx Spartan-3 architecture—just 96 slices (0.3% of an
XC3S5000 device) and 0.5 to 1 block RAM
•16 byte-wide general-purpose data registers
• 1K instructions of programmable on-chip program store, automatically loaded
during
FPGA configuration
• Byte-wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags
• 64-byte internal scratchpad RAM
• 256 input and 256 output ports for easy expansion and enhancement
• Automatic 31-location CALL/RETURN stack
• Predictable performance, always two clock cycles per instruction, up to 200 MHz
or
100 MIPS in a Virtex-II Pro FPGA
• Fast interrupt response; worst-case 5 clock cycles
• Support in Spartan-6, and Virtex-6 FPGA architectures
• Assembler, instruction-set simulator support
29
Block diagram
30
Example, external multiplier
31
PicoBlaze, in VHDL
processor: kcpsm
port map( address => address_signal,
instruction => instruction_signal,
port_id => port_id_signal,
write_strobe => write_strobe_signal,
out_port => out_port_signal,
read_strobe => read_strobe_signal,
in_port => in_port_signal,
interrupt => interrupt_signal,
reset => reset_signal,
clk => clk_signal);
32
PB, assembler
33
PB, data moving
34
MicroBlaze – cache memory
• Small cache memory is much quicker than external memory
•For the MB it is better to use internal BRAM memory (in the case
when data moving is easily determined) than cache as BRAM as
quick as cache memory but consumes less recourses
35
cache block structure
This structure is for tutorial-pupose only (not used in
real applications)
Data 0
Address 0
Valid-bit
=
Address
Data
Data 1
Address 1
Valid-bit
=
Data N
Address N
Valid-bit
=
36
Real Application
37
The End
38
Uproszczony przykład działania
Linie adresowe:
a30-a31 – ignorowane – dane są 4 bajtowe
Pamięć Tag
CacheL. DanaTag Cache adr
0
0x00
0x0000
1
0x00
0x0004
2
0x00
0x0008
3
0x03
0x030C
4
0x03
0x0310
5
0x05
0x0514
6
0x06
0x0618
7
0x07
0x071C
...
a24-a29 – linie adresowe pamięci tag i danych
(instrukcji)
a0-a23 – linie adresowe zapisywane w pamięci tag i
wykorzystywane podczas porównywania
39
LMB (Local Memory Bus) Sygnały
40
LMB (odczyt i zapis)
41
LMB szybki odczyt
42