1
Contents Reviewed
• Rabaey CH 3, 4, and 6
2
Physical Structure of MOS
Transistors: the NMOS
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
3
The PMOS Transistor
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
4
The CMOS Technology
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
5
Threshold Voltage Concept
+
S
VGS
-
D
G
n+
n+
n-channel
Depletion
Region
p-substrate
B
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
6
Current-Voltage Relations
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
7
Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
8
2-D Representation of MOS
Transistor
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
9
Switch-Level View of NMOS &
PMOS
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
10
CMOS Switch
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
11
CMOS Inverter
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
12
CMOS Inverter Layout
VDD
PMOS
1.2mm
=2l
In
Out
Metal1
Polysilicon
NMOS
GND
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
13
NMOS Switches in Series
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
14
PMOS Switches in Series
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
15
Switches in Parallel
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
16
2-Input CMOS NAND Gate: the
Switch View
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
17
2-Input CMOS NAND Gate: the
Circuit View
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
18
N-input CMOS NAND Gate
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
19
4-Input NAND Gate
Vdd
VDD
VDD
In1
In2
In3
In4
Out
In1
In2
Out
In3
Out
In4
GND
In1 In2 In3 In4
GND
In1 In2 In3 In4
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
20
2-Input CMOS OR-Gate
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
21
N-Input CMOS OR-Gate
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
22
Properties of CMOS Gates
• Vdd and GND are never directly
connected
• i.e. no shorting
• Output is always connected to either Vdd
or GND
• i.e. it never floats
23
Making Compound Gates in
CMOS
F = ((A.B) + (C.D))
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
24
Key Idea in CMOS Compound
Logic Gates
VDD
In1
In2
In3
PUN
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
25
More on CMOS Logic Style
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
26
Pull-Up and Pull-Down Circuits
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
27
CMOS Compound Gate
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
28
What is this?
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
29
How do we implement these?
• Z = (A.B.C.D)’
• Z = ((A.B) + C.(A+B))’
• Z = A.B + A’.B’
• what is this?
• Z = A.B’.C’ + A’.B’.C + A’.C’.B + A.B.C
• what is this?
30
A 2-Input CMOS Multiplexer
Output = A.S + B.S’
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
31
How can one implement
multiplexer using CMOS gates?
32
Layout: the Standard Cell
Approach
metal1
VDD
Well
VSS
Routing Channel
signals
polysilicon
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
33
Two versions of a.(b+c)
VDD
VDD
x
x
GND
a
c
b
(a) Input order {a c b}
GND
a
b
c
(b) Input order {a b c}
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
34
Logic Graph
VDD
x
b
j
c
c
a
PUN
i
x
VDD
x
b
c
j
a
PDN
i
GND
a
b
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
35
Consistent Euler Path
x
c
i
x
b
VDD
a
j
GND
{ a b c}
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
36
Example: x = ab + cd
x
x
c
b
VDD
x
a
c
b
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d}
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
37
Existence of Consistent Euler
Paths
• May depend on the way the Boolean
expression is written
• Example:
• x = (A + B.C + D.E)’ has no consistent Euler paths
• But,
• x = (B.C + A + D.E)’ does
38
Memory & Storage in CMOS
39
A CMOS Positive LevelSensitive D Latch
[Adapted from Principles of CMOS VLSI Design by Weste & Eshraghian]
40
A CMOS Positive EdgeTriggered D Register
41
Performance Analysis
of CMOS Gates
42
MOS Transistors are not “Ideal”
Switches
|V GS|
Ron
|VGS| < |VT|
|VGS| > |VT|
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
43
CMOS Inverter: A More Detailed
View
VDD
Vin
Vout
CL
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
44
CMOS Inverter: Steady State
Response
VDD
VDD
Ron
VOH = VDD
Vout
Vout
VM = f(Ronn,Ronp)
Ron
Vin = V DD
VOL= 0
Vin = 0
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
45
CMOS Inverter: Transient
Response
VDD
tpHL = f(R on.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
t
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
46
What is the value of Ron?
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
47
Numerical Examples for 1.2mm
CMOS
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
48
Transistor Sizing
• for symmetrical response (dc, ac)
• for performance
VDD
B
12
C
12
6
A
Input Dependent
Focus on worst-case
D
6
F
A
D
2
1
B
2 C
2
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
49
Propagation Delay Analysis
RON
=
VDD
VDD
Rp
Rp
A
B
F
F
A
CL
Rn
B
Rp
CL
Rn
A
(a) Inverter
Rp
Rp
B
A
Rn
VDD
(b) 2-input NAND
A
F
Rn
Rn
A
B
CL
(c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
50
Analysis of Propagation Delay
VDD
Rp
A
1. Assume Rn =Rp = resistance of minimum
sized NMOS inverter
Rp
B
F
Rn
B
Rn
A
CL
2. Determine “Worst Case Input” transition
(Delay depends on input values)
3. Example: tpLH for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
tpLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
51
Design for Worst Case
V DD
VDD
1
A
1
F
2
B
CL
4
C
4
2
A
B
B
D
2
F
A
2
A
D
2
1
B
2C
2
Here it is assumed that Rp = Rn
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
52
Influence of Fan-in and Fan-out
on Delay
VDD
A
B
C
D
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
A
B
C
D
FanIn: Quadratic Term due to:
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
tp = a1 FI + a2 FI 2 + a3 FO
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
53
tp as a Function of Fan-in
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
1
3
5
fan-in
7
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
54
Fast Complex Gates - I
• Transistor Sizing:
As long as Fan-out Capacitance dominates
• Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Distributed RC-line
Can Reduce Delay with more than 30%!
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
55
Fast Complex gates - II
• Transistor Ordering
critical path
critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
56
Fast Complex Gates - III
• Improved Logic Design
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
57
Fast Complex Gates - IV
• Buffering: Isolate Fan-in from Fan-out
CL
CL
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
58
Example: Full Adder
VDD
VDD
Ci
A
A
B
B
A
B
Ci
A
B
VDD
X
Ci
Ci
A
S
Ci
A
B
B
VDD
A
B
Ci
Co
A
B
Co = AB + C i(A+B)
28 transistors
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
59
Revised Full Adder
V DD
VDD
A
B
A
V DD
A
B
B
Ci
B
Kill
"0"-Propagate
A
Ci
Ci
Co
S
Ci
A
"1"-Propagate
Generate
A
B
B
A
B
Ci
A
B
24 transistors
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]