DSP C5000
Chapter 9
Understanding and Programming the
Multi-channel Buffered Serial Port
(McBSP)
Copyright © 2003 Texas Instruments. All rights reserved.
Outline
Application of McBSP
McBSP on
C5416 and C5510
Differences between C5416 and C5510
Configuration with CSL
References
ESIEE, Slide 2
Copyright © 2003 Texas Instruments. All rights reserved.
Application of McBSP

McBSP = Multichannel Buffered Serial Port



Direct interface to industry-standard codecs,
analog interface chips (AICs), and other serially
connected A/D - D/A and serial devices.
Direct connection to other C5000 devices,
Usually works in connection with DMA
Input or Output buffer
EF01
DMA
E23A
D6C5
McBSP
Serial device
Data
Clock
Frame Sync
Int./Ext. Memory
ESIEE, Slide 3
Copyright © 2003 Texas Instruments. All rights reserved.
Audio System using DMA and McBSP
Codec
A/D
DSP
SP
DMA
Mem
Sample Ready
Buffers Ready
D/A
SP
DMA
Application
Mem
Let’s take a closer look at how the buffers are organized...
ESIEE, Slide 4
Copyright © 2003 Texas Instruments. All rights reserved.
Ping-Pong Buffers
ping_RX
DMA

In order to make the application less
real-time critical, the input is double
buffered

These buffers are called ping-pong
buffers

The configuration is that of a two
frame circular buffer

First fill one buffer, then fill the other,
then switch back to the first
pong_RX
What about the output buffers?
ESIEE, Slide 5
Copyright © 2003 Texas Instruments. All rights reserved.
The Flow 1 of 4
ping_RX
ping_TX
Application
DMA INT
PING_TO_PONG
DMA
DMA
pong_RX
pong_TX
DMA INT
What needs to happen to the DMA Channels?
ESIEE, Slide 6
Copyright © 2003 Texas Instruments. All rights reserved.
The Flow 2 of 4
What buffers can the application use to process?
ESIEE, Slide 7
Copyright © 2003 Texas Instruments. All rights reserved.
The Flow 3 of 4
How do we know when new buffers are ready?
ESIEE, Slide 8
Copyright © 2003 Texas Instruments. All rights reserved.
The Flow 4 of 4
And everything starts over…on to the hardware!!
ESIEE, Slide 9
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP on C5416 and C5510

C5416 and C5510 McBSP are very
similar



3 McBSPs on C5416 and C5510
Basic pins on serial ports (R for Read
and X for Transmit):



ESIEE, Slide 10
The small differences will be discussed in a
later section
BDR or BDX: serial data
BCLKR or BCLKX: clock at bit rate
BFSR or BFSX: frame synchronization
(word rate)
Copyright © 2003 Texas Instruments. All rights reserved.
Multi-Channel Buffered Serial Port (McBSP)
RINT
McBSP
BDR
RSR
BDX
XSR
BCLKR
BCLKX
BFSR
BFSX
BCLKS



ESIEE, Slide 11
Clock
&
Frame
Control
RBR
DRR
DXR
XINT
Event
Data
Bus
DMA
Bus
CPU
DMA
MultiChannel
Control
Full duplex, max bit rate = ½ CPU clock
Word length: 8, 12, 16,20, 24, 32
Frame length (between FS): 1-128 words
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Interface Signals
Pin
BCLKR
BCLKX
BCLKS
BDR
BDX
BFSR
BFSX
ESIEE, Slide 12
I/O/Z†
Description
I/O/Z
Receive clock
I/O/Z
Transmit clock
I
External clock
I
Received serial data
O/Z
Transmitted serial data
I/O/Z
Receive frame synchronization
I/O/Z
Transmit frame synchronization
† I = Input, O = Output, Z = High-impedance
Copyright © 2003 Texas Instruments. All rights reserved.
More Features of the McBSP 1 of 2





Double-buffered transmission and
triple-buffered reception
Independent clocking and framing for
transmit and receive.
Capability to send interrupts to the
CPU and DMA event to the DMA
controller.
External shift clock generation or an
internal programmable-frequency clock
Highly programmable internal clock
and frame generation


ESIEE, Slide 13
Programmable sample rate generator
128 channels.
Copyright © 2003 Texas Instruments. All rights reserved.
More Features of the McBSP 2 of 2



Programmable polarity for both frame
synchronization and data clocks
8-bit data transfers with option of LSB
or MSB first
-Law and A-Law companding
RSR1
DR
(1)
(2) (DLB)
DX
ESIEE, Slide 14
8
RBR1
XSR1
8
16
Expand
Compress
16
RJUST
DXR1
16
DRR1
To CPU/DMA
From CPU/DMA
Copyright © 2003 Texas Instruments. All rights reserved.
Bit Ordering


Normally, transfers using the McBSP
are sent and received with the MSB
first.
Certain 8-bit data protocols (that do not
use companded data) require the LSB to
be transferred first:



ESIEE, Slide 15
By setting (R/X)COMPAND = 01b in
(R/X)CR2, the bit ordering of 8-bit words
is reversed (LSB first) .
This feature is only enabled if the
appropriate (R/X)WDLEN[1,2] is set to 0,
(8-bit words).
If either phase of the frame does not have
an 8-bit word length, the McBSP assumes
the word length is 8 bits, and LSB-first
ordering is done.
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Data and Control Paths
The letter B
before the
pin names is
omitted on
this figure,
ie DX
instead of
BDX.
It will also
be the case
in the
following
slides.
ESIEE, Slide 16
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Control Registers for Clock and Frame
Synchronisation and Control
SPCR1x
SPCR2x
RCR1x
RCR2x
XCR1x
XCR2x
SRGR1x
SRGR2x
PCRx
McBSP
McBSP
McBSP
McBSP
McBSP
McBSP
McBSP
McBSP
McBSP
serial port control register 1
serial port control register 2
receive control register 1
receive control register 2
transmit control register 1
transmit control register 2
sample rate generator register 1
sample rate generator register 2
pin control register
The x at the end of a register name represents the number of the
McBSP device: McBSP 0,1 or 2.
ESIEE, Slide 17
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Control Registers for Channel Selection

8 partitions A, B, C, D, E, F, G, H
MCR1x
MCR1x
RCERAx
RCERBx
RCERCx to
RCERHx
XCERAx
XCERBx
XCERCx to
XCERHx
McBSP multichannel register 1
McBSP multichannel register 2
McBSP receive channel enable register partition A
McBSP receive channel enable register partition B
…
McBSP transmit channel enable partition A
McBSP transmit channel enable partition B
...
The x at the end of a register name represents the number of the
McBSP device: McBSP 0,1 or 2.
ESIEE, Slide 18
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Configuration

Via SPCR1, SPCR2 and PCR registers


These contain status information and bits
that can be configured for the required
operation.
PCR


ESIEE, Slide 19
Configures the McBSP pins as inputs or outputs
during normal serial port operation,
Configures the pins as general purpose inputs or
outputs during receiver and/or transmitter reset.
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of McBSP, SPCR1 Register
15
DLB
RW,+0
7
DXENA
RW,+0
14
13
12
RJUST
RW,+0
6
ABIS
RW,+0
11
10
CLKSTP
RW,+0
5
4
RINTM
RW,+0
8
reserved
R,+0
3
RSYNCERR
RW,+0
2
RFULL
R,+0
1
RRDY
R,+0
0
RRST
RW,+0 *
Note: R = Read, W = Write, +0 = Value at reset
* R, +0 means read-only, reset value is 0. RW, +0 means read and write allowed, reset value is 0.










ESIEE, Slide 20
DLB= Digital Loop Back Mode
RJUST = Receive Sign-Extension and Justification Mode
CLKSTP = Clock Stop Mode
DXENA = DX delay Enabler
ABIS = A-bis mode
RINTM = Receive Interrupt Mode
RSYNCERR = Receive Synchronization Error
RFULL = Receiver shift Register full
RRDY = Receiver Ready
RRST = Receiver Reset
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of McBSP, SPCR2 Register
15
14
13
12
11
10
9
FREE
RW,+0
8
SOFT
RW,+0
4
3
XSYNCERR‡
RW,+0
2
XEMPTY
R,+0
1
XRDY
R,+0
0
XRST
RW,+0
Reserved*
R,+0
7
FRST
RW,+0
6
GRST
RW,+0
5
XINTM
RW,+0
*Note: This and all reserved bit-fields have NO storage associated with them; however, they are always read as 0.
‡ CAUTION: Writing a 1 to this bit sets the error condition; thus, it is mainly used for testing purposes or if this
operation is desired.




ESIEE, Slide 21
FREE = Free Running mode (in emulation)
SOFT = Soft bit (in emulation)
FRST = Frame-sync generator Reset
GRST = Sample rate generator Reset
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of McBSP
PCR Pin Control Register
15
14
13
XIOEN
RW,+0
12
RIOEN
RW,+0
11
FSXM
RW,+0
10
FSRM
RW,+0
9
CLKXM
RW,+0
8
CLKRM
RW,+0
6
CLKS STAT
R,+0
5
DX STAT
R,+0
4
DR STAT
R,+0
3
FSXP
RW,+0
2
FSRP
RW,+0
1
CLKXP
RW,+0
0
CLKRP
RW,+0
Reserved
R,+0
7
reserved
R,+0









ESIEE, Slide 22
XIOEN = Transmit general purpose IO mode
RIOEN = Receive general purpose IO mode
FSXM = Transmit Frame-Synchronization Mode
FSRM = Receive Frame-Synchronization Mode
CLKXM, CLKRM = Transmitter (Receiver) clock Mode
CLKS_STAT = Status of CLKS pin when GPIO
DX_STAT, DR_STAT = Status of DX (DR) when GPIO
FSXP, FSRP = Transmit (receive) Frame-Sync. Polarity
CLKXP, CLKRP = Transmit (receive) Clock Polarity
Copyright © 2003 Texas Instruments. All rights reserved.
Receive and Transmit Control Registers RCR and XCR
RCR1
15
rsvd
R,+0
14


13
12
11
10
RFRLEN1
RW,+0
9
8
7
6
5
RWDLEN1
RW,+0
4
3
2
1
Reserved
R,+0
0
RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame)
RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits)
RCR2
15
RPHASE
RW,+0
14
13

RPHASE = Receive phases (single or dual frames)
RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame)
RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits)
RCOMPAND = Receive companding mode
RFIG = Receive Frame Ignore
RDATDLY =Receive Data Delay





12
11
10
RFRLEN2
RW,+0
9
8
7
6
5
RWDLEN2
RW,+0
4
3
2
RCOMPAND RFIG
RW,+0
RW,+0
1
0
RDATDLY
RW,+0
Structure of XCR1 and XCR2 is similar to that of RCR1 and RCR2.
ESIEE, Slide 23
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Reset




ESIEE, Slide 24
(R/X)RST and RESET
Device reset (RS = 0) places the receiver,
transmitter and the sample rate generator
SRGR in reset.
When the device reset is removed (RS = 1)
GRST = FRST = RRST = XRST = 0,
keeping the entire serial port in the reset
state.
The SP transmitter and receiver can be
independently reset by the RRST and
XRST bits in the SPCR registers. The
SRGR is reset by the GRST bit in SPCR2.
Copyright © 2003 Texas Instruments. All rights reserved.
Determining Ready Status


RRDY and XRDY indicate the ready
state of the McBSP receiver and
transmitter.
Serial port writes and reads may be
synchronized:


By polling RRDY and XRDY,
or by using the events to DMA




ESIEE, Slide 25
REVT and XEVT in normal mode,
and REVTA and XEVTA in A-bis mode,
or by interrupts to CPU (RINT and XINT),
which the events generate.
Note that reading DRR[1,2] and writing to
DXR[1,2] affect RRDY and XRDY.
Copyright © 2003 Texas Instruments. All rights reserved.
Frame and Clock Configuration

The McBSP allows independent
configurations of data clock and frame
synchronization for receive and transmit:








ESIEE, Slide 26
Polarities of FSR, FSX, CLKX, and CLKR
A choice of single- or dual-phase frames
For each phase, the number of words per frame
For each phase, the number of bits per word
Subsequent frame synchronization may restart the
serial data stream or be ignored.
The data bit delay from frame synchronization to
first data bit can be 0-,
1-, or 2-bit delays.
Right- or left-justification as well as sign-extension
or zero-filling can be chosen for receive data.
Copyright © 2003 Texas Instruments. All rights reserved.
Frame and Clock Operation

Receive and transmit frame-sync pulses
can be generated:





ESIEE, Slide 27
Either internally by the sample rate
generator SRGR,
or driven by an external source.
The source of frame sync is selected by the
mode bit, FS(R/X)M, in the PCR.
FSR is affected by GSYNC bit in SRGR2
Receive and transmit clocks can be selected
to be inputs or outputs by the mode bit,
CLK(R/X)M, in the PCR.
Copyright © 2003 Texas Instruments. All rights reserved.
Sample Rate Generator
ESIEE, Slide 28
Copyright © 2003 Texas Instruments. All rights reserved.
Sample Rate Generator Register SRGR
SRGR 1
15
8
7
0
FWID
RW,+0
CLKGDV
RW
FWID = Frame Width
CLKGDV = Sample rate generator Clock Divider


SRGR 2
15
14
13
12
GSYNC CLKSP CLKSM FSGM
RW,+0 RW,+0
RW
RW,+0





ESIEE, Slide 29
11
10
9
8
7
6
5
FPER
RW,+0
4
3
2
1
0
GSYNC = SRGR Clock synchronization
CLKSP = Polarity Clock edge selection
CLKSM = SRGR Clock Mode
FSGM = SRGR transmit Frame-Sync Mode
FPER = Frame Period
Copyright © 2003 Texas Instruments. All rights reserved.
Data Clock Generation

When (CLK[R/X]M = 1), the data
clocks (CLK[R/X]) are driven by:


the internal SRGR output clock, CLKG.
The input clock to the SRGR can be either
the CPU clock or a dedicated external
clock input (CLKS).



ESIEE, Slide 30
The CLKSM bit in SRGR2 selects either the
CPU clock (CLKSM = 1) or the external clock
input (CLKSM = 0) CLKS.
The input clock source to the SRGR can be
divided down by a programmable value
(CLKGDV) to drive CLKG
Regardless of the source to the SRGR, the
rising edge of CLKSRG generates CLKG
and FSG
Copyright © 2003 Texas Instruments. All rights reserved.
Digital Loop Back Mode DLB




ESIEE, Slide 31
DLB = 1 in SPCR1 enables digital loop
back mode.
During DLB mode, DR, FSR, and
CLKR are internally connected through
multiplexers to DX, FSX, CLKX,
respectively.
DLB mode allows testing of serial port
code with a single DSP device.
In digital loop back mode, the
transmitter clock drives the receiver.
CLKRM determines whether the CLKR
pin is an input or an output.
Copyright © 2003 Texas Instruments. All rights reserved.
Frame-sync Signal Generation


When FRST=1 in SPCR2, it activates
the frame-sync generation logic to
generate a frame-sync signal, if FSGM =
1 in SRGR2.
Frame-sync programming options:



ESIEE, Slide 32
A frame pulse with a programmable period
and programmable active width, using the
SRGR1 register,
The transmit portion may trigger its own
frame-sync signal generated by a
DXR[1,2]-to-XSR[1,2] copy,
Both the receive and transmit sections may
independently select an external frame
synchronization on the FSR and FSX pins,
respectively.
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP - Example

Problem: transfer 16 16-bit words to SARAM, ext’l CLK/FS, no CPU int
SARAM
A/D
D
CLK
FS
1
SPCR1 5
1
PCR 5
McBSP
w15
...
w1
w0
4
5
ESIEE, Slide 33
DRR
RINTM
RRDY
CPU interrupt?
DRR ready?
(not used)
(not used)
1
0
FSR
8
0
- RSR  RBR
0
CLKRM
1-128
(16)
5
RWDLEN1
8/12/16/20/24/32
(16)
- RBR  DRR (RRDY=1)
- REVT sync event activates
DMA (no McBSP setup)
1-internal
7
Operation
- Bit/CLKR shifted into RSR
M
0-external
0-external
1
8
4
RFRLEN1
DMA
REVT
1
1-internal
1
RCR1 5
BDR
CLKR
FSR
0
1
...
15
0
- DMA transfers DRR
to SARAM
…repeat
Copyright © 2003 Texas Instruments. All rights reserved.
Multichannel Selection Operation

A McBSP channel is a time slot for shifting
in/out the bits of one serial word.


The 128 channels are divided into 8 blocks
of 16 consecutive channels:




Block 0: Channels 0-15
Block 1: Channels 16-31 …
Block 7: Channels 112-127
The blocks are assigned to partitions:


ESIEE, Slide 34
Each McBSP supports up to 128 channels.
In ‘C5410 or ‘C5420, only 2 partitions A or B
In the C5416 and C5510, choice between 2
partitions (A,B) or 8 partitions (A, B, C, …H.)
Copyright © 2003 Texas Instruments. All rights reserved.
Multichannel Partition Mode

In the 2 partitions mode:



In the 8 partitions mode, blocks 0
through 7 are automatically assigned to
partitions A through H.


ESIEE, Slide 35
One even-numbered block (0,2,4,6) is
assigned to partition A and one oddnumbered block (1,3,5,7) to partition B.
Up to 32 channels can be selected.
Up to 128 channels can be selected.
The number of partitions for reception
and transmission are independent.
Copyright © 2003 Texas Instruments. All rights reserved.
Multichannel Selection


When a McBSP uses a TDM (Time
Division Multiplex) data stream, it may
need to select only a few channels to
save memory and bandwidth.
Each channel partition has a dedicated
channel enable register.


ESIEE, Slide 36
If the multichannel selection mode is on,
each bit in the register controls whether a
channel is selected or not in the partition.
There is 1 receive multichannel selection
mode and 3 transmit modes.
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring a Frame for Multichannel
Selection

Select a single-phase frame:



ESIEE, Slide 37
RPHASE/WPHASE = 0
Each frame represents a TDM data stream.
Set a frame length (R/X)FRLEN1
including the highest-numbered channel
in the selection.
Copyright © 2003 Texas Instruments. All rights reserved.
Control of Multichannel Selection


The multichannel mode can be enabled
independently for receive and transmit
by setting RMCM = 1 and XMCM to a
non-zero value in control registers
MCR[1,2], respectively.
Choose the partition mode: 2 or 8
partitions, with the RMCME and/or
XMCME bits:


ESIEE, Slide 38
(R/X)MCME = 0, 2 partitions A-B
(R/X)MCME = 1, 8 partitions A-B…H
Copyright © 2003 Texas Instruments. All rights reserved.
Multichannel Operation Control Registers


MCR1, MCR2: Multichannel control
registers
XCERx: transmit channel enable registers


RCERx: receive channel enable registers

ESIEE, Slide 39
x = a letter A, B, C, D, E, F or H
x = a letter A, B, C, D, E, F or H
Copyright © 2003 Texas Instruments. All rights reserved.
Multichannel Operation MCR1 Register
MCR1 for C5410 or C5420
15
14
13
12
Reserved
R,+0




11
10
9
8
7
RPBBLK
RW,+0
6
5
RPABLK
RW,+0
4
3
RCBLK
R,+0
2
1
0
rsvd RMCM
R,+0 RW,+0
RPBBLK = Receive Partition B Block
RPABLK = Receive Partition A Block
RCBLK = Receive Current Block
RMCM = Receive Multichannel Selection Enable
MCR1 for C5416 and C5510
15
14

ESIEE, Slide 40
13
12
Reserved
R,+0
11
10
9
RMCME
8
7
RPBBLK
RW,+0
6
5
RPABLK
RW,+0
4
3
RCBLK
R,+0
2
1
0
rsvd RMCM
R,+0 RW,+0
RMCME = Receive Multichannel Partition Mode bit, applicable if
channel can be individually selected RMCM = 1
Copyright © 2003 Texas Instruments. All rights reserved.
Multichannel Operation MCR2 Register

15
14
MCR2 has the same structure as MCR1 but for transmission.
MCR 2 for C5410 or C54 20
13
12
Reserved
R,+0
11
10
9
8
7
XPBBLK
RW,+0
6
5
XPABLK
RW,+0
4
3
XCBLK
R,+0
4
3
XCBLK
R,+0
2
1
0
XMCM
RW,+0
MCR 2 for C5416 and C5510
15
14
13
12
Reserved
R,+0

The XMCM bits of XCR2 determine whether all channels or only
selected channels are enabled and unmasked for transmission.
There are 3 transmit multichannel selection modes





ESIEE, Slide 41
11
10
9
XMCME
8
7
XPBBLK
RW,+0
6
5
XPABLK
RW,+0
2
1
0
XMCM
RW,+0
00b: No selection. All channels are enabled and unmasked.
01b: All channels are disabled unless selected in XCERs registers. If
enabled, a channel is also unmasked.
10b: All channels are enabled, but they are masked unless they are
selected in XCERs registers.
11 b: symmetric transmission/reception. All channels are disabled for
transmission unless they are enabled for reception in RCER registers.
Once enabled, they are masked unless they are also selected in the
XCERs registers.
Copyright © 2003 Texas Instruments. All rights reserved.
Using 2 partitions A and B

McBSP channels are activated using an
alternating scheme. After a sync pulse:


Assigning blocks to partitions. Any 2 of
the 8 blocks can be assigned to A and B:


ESIEE, Slide 42
Receiver or transmitter begins with the
channels in partition A and alternates
between part. B and A until the end of the
frame.
Assign an even-numbered block to A by
writing the 2 (R/X)PABLK bits and an
odd-numbered block to B (R/X)PBBLK.
The channels are controlled the receive or
transmit channel enable registers
(R/X)CERCA, (R/X)CERA.
Copyright © 2003 Texas Instruments. All rights reserved.
Using 2 partitions A and B

Blocks can be reassigned during
communication if we want to use more
than 32 selected channels.



ESIEE, Slide 43
It is not possible to modify the block
assignment of a partition during its
transfer.
The block currently involved in the
transmission is reflected in the (R/X)CBLK
bits. They can be polled.
At the end of a block, an interrupt can be
sent to the CPU that checks (R/X)CBLK
bits and updates the inactive partition.
Copyright © 2003 Texas Instruments. All rights reserved.
Using 8 Partitions


RMCME/XMCME = 1
Partitions are activated in the order:



The (R/X)PABLK and (R/X)PBBLK are
ignored.
The blocks are assigned to the partitions in
natural order:




ESIEE, Slide 44
A B C D E F G H.
A: block 0, channels 0 to 15, reg. (R/X)CERA
B: block 1, channels 16 to 31, reg. (R/X)CERB
…
H: block 7, chan. 112 to 127, reg. (R/X)CERH
Copyright © 2003 Texas Instruments. All rights reserved.
Receive Channels Disabled

If a receive channel is disabled, any bits
received in that channel are passed only
as far as the receive buffer register(s)
(RBR(s)).


ESIEE, Slide 45
The receiver does not copy the content of
the RBR(s) to the DRR(s), and as a result,
does not set the receiver ready bit (RRDY).
Therefore, no DMA synchronization event
(REVT) is generated, and if the receiver
interrupt mode depends on RRDY
(RINTM = 00b), no interrupt is generated.
Copyright © 2003 Texas Instruments. All rights reserved.
Enabling/Disabling versus Masking/Unmasking

For transmission, a channel may be:

Enabled and unmasked




Enabled and masked



Transmission can begin and be completed
Enabled: Data are passed from DXR to XSR.
Unmasked: Data in XSR shifted out on DX pin.
Transmission can begin but cannot be completed
Masked: DX pin is held in high impedance. Avoids
bus contention on a shared serial bus.
Disabled

Transmission cannot occur. No DXR to XSR copy.

ESIEE, Slide 46
The bit XRDY is not set.
Copyright © 2003 Texas Instruments. All rights reserved.
Channel Enable Registers RCERx and XCERx


In C5410 and C5420, there are 2 receive and 2 transmit
Channel Enable Registers: RCERA, RCERB, XCERA,
XCERB.
In C5416 and C5510, there are 8 receive + 8 transmit
Channel Enable Registers: RCERA to RCERH and
XCERA to XCERH.
RCERA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCEA15 RCEA14 RCEA13 RCEA12RCEA11 RCEA10 RCEA9 RCEA8 RCEA7 RCEA6 RCEA5RCEA4 RCEA3 RCEA2 RCEA1 RCEA0
RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0
XCERA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
XCEA15 XCEA14 XCEA13 XCEA12 XCEA11 XCEA10 XCEA9 XCEA8 XCEA7 XCEA6 XCEA5 XCEA4 XCEA3 XCEA2 XCEA1 XCEA0
RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0
ESIEE, Slide 47
Copyright © 2003 Texas Instruments. All rights reserved.
SPI Mode

The SPI protocol is a master-slave configuration, with one master
device and one or more slave devices. The interface consists of four
signals.

ESIEE, Slide 48
The clock stop mode of the McBSP provides compatibility with the SPI
protocol.
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Pins as General Purpose I/O pins 1 of 2

Two conditions allow the serial port pins
(CLKX, FSX, DX, CLKR, FSR and DR) to be
used as general purpose input/output (I/O)
rather than serial port pins:



In the case of FS(R/X), FS(R/X)M=0(or 1)
configures the pin as an input (or output).


ESIEE, Slide 49
1) The related portion (transmitter or receiver) of
the serial port is in reset; (R/X)RST = 0 in
SPCR[1,2].
2) General purpose I/O is enabled for the related
portion of the serial port; (R/X)IOEN = 1 in the
PCR.
When configured as an output, the value driven on
FS(R/X) is the value stored in FS(R/X)P.
If configured as an input, FS(R/X)P becomes a
read-only bit that reflects the status of that signal.
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Pins as General Purpose I/O pins 2 of 2


CLK(R/X)M and CLK(R/X)P work
similarly for CLK(R/X).
DX and DR as GPIO pins:



CLKS as a general purpose input:

ESIEE, Slide 50
the value of the DX_STAT bit in the PCR is
driven onto DX.
DR is always an input and its value is held
in the DR_STAT bit in the PCR.
both the transmitter and receiver must be
in reset state and (R/X)IOEN = 1, because
CLKS is always an input to the McBSP and
affects both transmit and receive
operations.
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Operation in Power-down Mode

For the C5416, Power-down modes may be
invoked in several ways:




executing the IDLE instruction or driving the
HOLD input low with the HM status bit set to one.
The McBSP can take the CPU out of IDLE using a
transmit or receive interrupt.
When in IDLE1 or HOLD modes, the McBSP
continues to operate normally with no restrictions.
In IDLE2 or IDLE3 modes, the internal device
clocks provided to the peripherals are stopped.



ESIEE, Slide 51
If external clock and frame-sync are provided, the
McBSP can continue to operate, and receive and
transmit interrupts can be used to exit the IDLE state.
If either clocks or frame-syncs are internal, the McBSP
will stop in IDLE2/3.
In IDLE2/3, the internal clocks to the McBSP and the
DMA controller are started automatically when a
transfer begins, and stopped after the transferis
completed.
Copyright © 2003 Texas Instruments. All rights reserved.
McBSP Operation in Power-down Mode

For the C5510, The McBSP is placed into its
idle mode when:



In the McBSP idle mode:


ESIEE, Slide 52
the PERIPH idle domain is idle (PERIS = 1 in
ISTR)
the McBSP idle enable bit is set (SPn = 1) in the
PICR register. When the McBSP is in the Idle
state, it is unable to receive or transmit data.
If the McBSP is operates with internal clocking
and frame sync., it will be completely stopped.
If the McBSP is operates with ext. clocking and
frame sync., the external interface portion of the
McBSP continues to function during external
clock activity periods. The McBSP sends a request
to activate the PERIPH and DMA idle domains
when it needs to be serviced. If the domains were
idle, they are made idle again after the McBSP has
been serviced.
Copyright © 2003 Texas Instruments. All rights reserved.
Emulation FREE and SOFT Bits

FREE and SOFT are special emulation bits
that determine the state of the serial port
clock when a breakpoint is encountered in the
high-level language debugger.

If the FREE bit is set to 1





ESIEE, Slide 53
upon a software breakpoint, the clock continues to run
(free runs) and data still shifts out. When FREE = 1, the
SOFT bit is a don’t care.
If the FREE bit is cleared to zero, then the SOFT
bit takes effect.
If the SOFT bit is cleared to zero, then the clock
stops immediately, thus aborting a transmission.
If the SOFT bit is set to one and a transmission is
in progress, the transmission continues until
completion of the transfer, and then the clock
halts.
The receiver-side functions in a similar fashion.
Copyright © 2003 Texas Instruments. All rights reserved.
Differences Between C5416 and C5510 McBSP

Addressing of McBSP registers:

C5416: sub-bank system


C5416 McBSP
Registers addr.



ESIEE, Slide 54
Some registers are mapped in data memory page 0:
DRR, DXR + SPSA and SPSD
SPSAx: McBSP Sub-Address register associated with a
SPSD Sub-bank Data register containing the value for one
of the sub-bank registers
The other registers are sub-bank registers accessed
by sub-addresses relative to SPSA.
C5510: Registers are mapped in the I/O space
Power-down modes
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of the McBSP 1 of 3

ESIEE, Slide 55
Receiver/transmitter configuration
Place the McBSP receiver /
transmitter in reset
Program the McBSP registers for the
desired receiver / transmitter
operation
Take the receiver / transmitter out of
reset
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of the McBSP 2 of 3

Global behavior





Data behavior








ESIEE, Slide 56
Set the receiver pins to operate as McBSP pins
Enable/disable the digital loopback mode
Enable/disable the clock stop mode
Enable/disable the receive multichannel selection
mode
Choose 1 or 2 phases for the receive frame
Set the receive word length(s)
Set the receive frame length
Enable/disable the receive frame-sync ignore function
Set the receive companding mode
Set the receive data delay
Set the receive sign-extension and justification mode
Set the receive interrupt mode
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of the McBSP 3 of 3

Frame-sync behavior




Clock behavior






ESIEE, Slide 57
Set the receive frame-sync mode
Set the receive frame-sync polarity
Set the SRG frame-sync period and pulse
width
Set the receive clock mode
Set the receive clock polarity
Set the SRG clock divide-down value
Set the SRG clock synchronization mode
Set the SRG clock mode [choose an input
clock]
Set the SRG input clock polarity
Copyright © 2003 Texas Instruments. All rights reserved.
Configuration of the McBSP with CSL

Example of the DSK-CCS tutorial
audioIO.c of Chapter 4 for the ‘C5416.



First we examine the file audioIOcfg_c.c
that configures the DSP,
Then we explain how to automatically
generate it with the GUI interface of CCS.
Parameters:




List of files of the example to examine


ESIEE, Slide 58
The McBSP 2 is used
Single phase mode
32 bits words.
audioIOcfg.h
audioIOcfg_c.c
Copyright © 2003 Texas Instruments. All rights reserved.
File audioIOcfg.h
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten.
*/
/* INPUT audioIO.cdb */
#define CHIP_5416 1
/* Include Header Files */
#include <std.h>
#include <hst.h>
#include <swi.h>
#include <tsk.h>
#include <log.h>
#include <sts.h>
#include <csl_mcbsp.h>
#ifdef __cplusplus
extern "C" {
#endif
extern HST_Obj RTA_fromHost;
extern HST_Obj RTA_toHost;
extern SWI_Obj KNL_swi;
extern TSK_Obj TSK_idle;
extern LOG_Obj LOG_system;
extern STS_Obj IDL_busyObj;
extern MCBSP_Config mcbspCfg0;
extern MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp;
extern void CSL_cfgInit();
Includes the Chip Support
Library for the McBSP
Defines variables
#ifdef __cplusplus
}
#endif /* extern "C" */
ESIEE, Slide 59
Copyright © 2003 Texas Instruments. All rights reserved.
Example of McBSP configuration file
1st part of the file audioIOcfg_c.c
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten.
*/
/* INPUT audioIO.cdb */
/* Include Header File */
#include "audioIOcfg.h"
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x0000,
/* Serial Port Control Register 1 */
SPCR1=0, SPCR2=0x200
0x0200,
/* Serial Port Control Register 2 */
0x00a0,
/* Receive Control Register 1 */
RCR1=0x00a0, RCR2=0
0x0000,
/* Receive Control Register 2 */
0x00a0,
/* Transmit Control Register 1 */
XCR1=0x00a0, XCR2=0
0x0000,
/* Transmit Control Register 2 */
0x1f00,
/* Sample Rate Generator Register 1 */
SRGR1=0x1f00, SRGR2=0x003f
0x003f,
/* Sample Rate Generator Register 2 */
0x0000,
/* Multichannel Control Register 1 */
MCR1=0x0000, MCR2=0x0000
0x0000,
/* Multichannel Control Register 2 */
0x0083,
/* Pin Control Register */
PCR=0x0083
0x0000,
/* Receive Channel Enable Register Partition A */
0x0000,
/* Receive Channel Enable Register Partition B */
0x0000,
/* Receive Channel Enable Register Partition C */
All receive channel enable
0x0000,
/* Receive Channel Enable Register Partition D */
registers RCERx are set
0x0000,
/* Receive Channel Enable Register Partition E */
to 0
0x0000,
/* Receive Channel Enable Register Partition F */
0x0000,
/* Receive Channel Enable Register Partition G */
0x0000,
/* Receive Channel Enable Register Partition H */
ESIEE, Slide 60
Copyright © 2003 Texas Instruments. All rights reserved.
Example of McBSP Configuration File
Last Part of the File
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000
/*
/*
/*
/*
/*
/*
/*
/*
Transmit Channel Enable Register Partition A
Transmit Channel Enable Register Partition B
Transmit Channel Enable Register Partition C
Transmit Channel Enable Register Partition D
Transmit Channel Enable Register Partition E
Transmit Channel Enable Register Partition F
Transmit Channel Enable Register Partition G
Transmit Channel Enable Register Partition H
*/
*/
*/
*/
*/
*/
*/
*/
All transmit channel
enable registers XCERx
are set to 0
};
/* Handles */
MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp;
/*
* ======== CSL_cfgInit() ========
*/
void CSL_cfgInit()
{
C54XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);
MCBSP_config(C54XX_DMA_MCBSP_hMcbsp, &mcbspCfg0);
}
Using CSL to open and initialise the McBSP 2.
ESIEE, Slide 61
Copyright © 2003 Texas Instruments. All rights reserved.
File audioIOcfg_c.c 1 of 3

SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control
Registers



RCR1 = 0x00A0, RCR2 = 0, Receive Control Registers








ESIEE, Slide 62
RJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0,
RRST=0
FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0
RWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frame
RDATDLY=0, 0 bit data delay
RFIG=0, received frame-sync not ignored
RCOMPAND=0, no companding
RWLEN2=0
RFRLEN2= 0
RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored.
XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR,
Transmit Control Register.
Copyright © 2003 Texas Instruments. All rights reserved.
File audioIOcfg_c.c 2 of 3

SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate
Generator Registers








ESIEE, Slide 63
CLKGDV =0, divide down value for CLKG
FWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG
cycles
FPER=0x3F=63, Frame-sync period bits for FSG, the period
between frame-sync pulses on FSG is 64 CLKG cycles.
FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync
pulse when DXR is copied in XSR. But here FSXM=0 (see PCR).
CLKSM=0, the input clock for SRGR is taken on CLKS pin or
CLKR pin depending on SCLKME bit in PCR. Here
SCLKME=1=signal on CLKR.
CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives
the clock signal CLKG and FSG.
GSYNC=0, no clock synchronization
MCR1 = 0, MCR2 = 0, no multichannel selection,
Multichannel Control Registers
Copyright © 2003 Texas Instruments. All rights reserved.
File audioIOcfg_c.c 3 of 3

PCR = 0x0083, Pin control Register

CLKRP=1, CLKXP=1, clock polarity











ESIEE, Slide 64
As CLKRM=0, CLKR is an input and the received data is
sampled on the rising edge of CLKR.
transmit data is driven on falling edge of CLKX.
FSRP=FSXP=0, frame-sync pulses are active high.
DRSTAT=0, DXSTAT=0, not applicable here.
CLKSTAT=0,not applicable here.
SCLKME=1, SRGR input clock is taken from CLKR pin
(CLKSM=0).
CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX
pins are inputs that suppies the internal clocks.
FSRM=FSXM=0, Receive and transmit frame-sync is
supplied by an ext source via FSR and FSX pins.
RIOEN=XIOEN=0, the McBSP pins are not GPIO pins
IDLEEN=0, the McBSP remains active when the PERIPH
domain is idled.
RCERx and XCREx = 0, There is no multichannel
selection
Copyright © 2003 Texas Instruments. All rights reserved.
Example using the ‘C5416 DSK 1 of 2

ESIEE, Slide 65
Create a new project iomcbsp.pjt and Create a new cdb file
Copyright © 2003 Texas Instruments. All rights reserved.
Example using the ‘C5416 DSK 2 of 2

Save (File>Save) the new configuration file
under the project directory: iomcbsp.cdb
Add to the project two of the files generated
at the previous step: the configuration file
(*.cdb) and the linker command file (*.cmd).
Copy the file audioIO.c of chapter ‘ example
in the project directory and rename it
iomcbsp.c
Modify the main source file: iomcbsp to
include the header file iomcbspcfg.h
generated at the configuration step
and add iomcbsp.c to the project.

Modify build options:





ESIEE, Slide 66
Project>Build Options to add the
dsk5416f.lib library and set use far calls.
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the McBSP
Configuration Manager of the CSL GUI
ESIEE, Slide 67
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 1 of 4
ESIEE, Slide 68
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 2 of 4
ESIEE, Slide 69
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 3 of 4
ESIEE, Slide 70
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 4 of 4

Modify:


« Receive Lengths », « Transmit Lengths » to set
word length to 32 bits
« Sample_Rate Gen »,




« Transmit Mode », clock polarity = falling edge
« General »


ESIEE, Slide 71
choose generator clock source=BCLKR
set frame width to 32 and frame period to 64.
Set Breakpoint Emulation to do not stop to set FREE = 1.
Save the new iomcbsp.cdb file and look at the
iomcbspcfg_c.c file. It should be quite similar to
the audioIOcfg_c.c file for the initialization
part.
Copyright © 2003 Texas Instruments. All rights reserved.
View of iomcbspcfg_c.c file at this Step
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten.
*/
/* INPUT iomcbsp.cdb */
/* Include Header File */
#include "iomcbspcfg.h"
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x0000,
/* Serial Port Control Register 1 */
0x0200,
/* Serial Port Control Register 2 */
0x00a0,
/* Receive Control Register 1 */
0x0000,
/* Receive Control Register 2 */
0x00a0,
/* Transmit Control Register 1 */
0x0000,
/* Transmit Control Register 2 */
0x1f00,
/* Sample Rate Generator Register 1 */
0x003f,
/* Sample Rate Generator Register 2 */
0x0000,
/* Multichannel Control Register 1 */
0x0000,
/* Multichannel Control Register 2 */
0x0083,
/* Pin Control Register */
0x0000,
/* Receive Channel Enable Register Partition A */
0x0000,
/* Receive Channel Enable Register Partition B */
0x0000,
/* Receive Channel Enable Register Partition C */
0x0000,
/* Receive Channel Enable Register Partition D */
0x0000,
/* Receive Channel Enable Register Partition E */
0x0000,
/* Receive Channel Enable Register Partition F */
0x0000,
/* Receive Channel Enable Register Partition G */
0x0000,
/* Receive Channel Enable Register Partition H */
0x0000,
/* Transmit Channel Enable Register Partition A */
0x0000,
/* Transmit Channel Enable Register Partition B */
0x0000,
/* Transmit Channel Enable Register Partition C */
0x0000,
/* Transmit Channel Enable Register Partition D */
0x0000,
/* Transmit Channel Enable Register Partition E */
0x0000,
/* Transmit Channel Enable Register Partition F */
0x0000,
/* Transmit Channel Enable Register Partition G */
0x0000
/* Transmit Channel Enable Register Partition H */
};
/* Handles */
/*
* ======== CSL_cfgInit() ========
*/
void CSL_cfgInit()
{
}
ESIEE, Slide 72
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the Resource
Manager of the CSL GUI


Use the McBSP Resource Manager
menu to generate the
MCBSP_open()and the
MCBSP_config() CSL functions.
It allows to select, open, initialize a
device



ESIEE, Slide 73
We select McBSP 2
We ask for the McBSP handle creation with
the name C54XX_DMA_MCBSP that will
be used by the routines of the BSL.
And we ask for the opening of the McBSP
handle and for the pre-initialization with
object mcbspCfg0.
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 1 of 4
ESIEE, Slide 74
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 2 of 4
ESIEE, Slide 75
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 3 of 4
ESIEE, Slide 76
Copyright © 2003 Texas Instruments. All rights reserved.
Configuring the McBSP using the CSL GUI 4 of 4


Save the file iomcbsp.cdb
Open the file iomcbspcfg_c.c

ESIEE, Slide 77
You should see the instructions for the
opening and initialization of the McBSP.
Copyright © 2003 Texas Instruments. All rights reserved.
Final version of the iomcbspcfg_c.c File
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten.
*/
/* INPUT iomcbsp.cdb */
/* Include Header File */
#include "iomcbspcfg.h"
/* Config Structures */
MCBSP_Config mcbspCfg0 = {
0x0000,
/* Serial Port Control Register 1 */
0x0200,
/* Serial Port Control Register 2 */
0x00a0,
/* Receive Control Register 1 */
0x0000,
/* Receive Control Register 2 */
0x00a0,
/* Transmit Control Register 1 */
0x0000,
/* Transmit Control Register 2 */
0x1f00,
/* Sample Rate Generator Register 1 */
0x003f,
/* Sample Rate Generator Register 2 */
0x0000,
/* Multichannel Control Register 1 */
0x0000,
/* Multichannel Control Register 2 */
0x0083,
/* Pin Control Register */
0x0000,
/* Receive Channel Enable Register Partition A */
0x0000,
/* Receive Channel Enable Register Partition B */
0x0000,
/* Receive Channel Enable Register Partition C */
0x0000,
/* Receive Channel Enable Register Partition D */
0x0000,
/* Receive Channel Enable Register Partition E */
0x0000,
/* Receive Channel Enable Register Partition F */
0x0000,
/* Receive Channel Enable Register Partition G */
0x0000,
/* Receive Channel Enable Register Partition H */
0x0000,
/* Transmit Channel Enable Register Partition A */
0x0000,
/* Transmit Channel Enable Register Partition B */
0x0000,
/* Transmit Channel Enable Register Partition C */
0x0000,
/* Transmit Channel Enable Register Partition D */
0x0000,
/* Transmit Channel Enable Register Partition E */
0x0000,
/* Transmit Channel Enable Register Partition F */
0x0000,
/* Transmit Channel Enable Register Partition G */
0x0000
/* Transmit Channel Enable Register Partition H */
};
/* Handles */
MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp;
/*
* ======== CSL_cfgInit() ========
*/
void CSL_cfgInit()
{
C54XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);
MCBSP_config(C54XX_DMA_MCBSP_hMcbsp, &mcbspCfg0);
}
ESIEE, Slide 78
Creation of the McBSP handle
Opening and initialization
of McBSP2
Copyright © 2003 Texas Instruments. All rights reserved.
Test the iomcbsp program



Build the project
Load iomcbsp.out in Program memory
Check the program


ESIEE, Slide 79
using a microphone (or a CD output) and
earphones, you should hear the input (mike
or CD) in the earphones (or loudspeaker).
Use tools>C54xx McBSP to view all the
registers of the McBSP.
Copyright © 2003 Texas Instruments. All rights reserved.
References

User’s guides

Spru302:



Tms320c5416.pdf
Spru592a:

ESIEE, Slide 80
TMS320C54x DSP Reference Set Volume 5:
Enhanced Peripherals.
TMS320VC5501/5502/5509/5510 DSP
Multichannel Buffered Serial Port (McBSP)
Reference Guide.
Copyright © 2003 Texas Instruments. All rights reserved.