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CHAPTER 8
Differential and Multistage Amplifiers
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Figure 8.1 The basic MOS differential-pair configuration.
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Figure 8.2 The MOS differential pair with a common-mode input voltage VCM.
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Figure 8.3 Circuits for Example 8.1. Effects of varying VCM on the operation of the differential pair.
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Figure 8.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2
operate when conducting drain currents equal to I/2, the equilibrium situation. Note that these graphs are universal and apply to any MOS
differential pair
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Figure 8.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV .
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Figure 8.10 (a) Differential amplifier for Example 8.2. (b) Differential half-circuit.
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Figure 8.11 (a) Differential amplifier with current-source loads formed by Q3 and Q4. (b) Differential half-circuit of the amplifier in (a).
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Figure 8.12 (a) Cascode differential amplifier; and (b) its differential half circuit.
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Figure 8.15 The basic BJT differential-pair configuration.
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Figure E8.9
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Figure 8.18 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the linear range of operation can be extended) by
including resistances in the emitters.
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Figure 8.21 A differential amplifier with emitter resistances. Only signal quantities are shown (in color).
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Figure 8.22 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers in (b). This equivalence applies only for
differential input signals. Either of the two common-emitter amplifiers in (b) can be used to find the differential gain, differential input
resistance, frequency response, and so on, of the differential amplifier.
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Figure 8.23 The differential amplifier fed in a single-ended fashion.
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Figure 8.24 Equivalent-circuit model of the differential half-circuit formed by Q1 in Fig. 8.22(b).
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Figure 8.26 (a) Definition of the input common-mode resistance Ricm . (b) The equivalent common-mode half-circuit.
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Figure 8.27 Circuit for Example 8.4.
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Figure 8.28 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO
results. (b) Application of a voltage equal to the input offset voltage VOS to the input terminals with opposite polarity reduces VO to zero.
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Figure 8.30 A three-stage amplifier consisting of two differential-in, differential-out stages, A1 and A2, and a differential-in, single-ended-out
stage A3.
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Figure 8.31 A simple but inefficient approach for differential to single-ended conversion.
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Figure 8.32 (a) The active-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching. (c) The circuit with a
differential input signal applied and neglecting the ro of all transistors.
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Figure 8.33 Output equivalent circuit of the amplifier in Fig. 8.32(a) for differential input signals.
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Figure 8.35 Circuit for determining Ro. The circled numbers indicate the order of the analysis steps.
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Figure 8.36 Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain.
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Figure 8.38 Analysis of the bipolar active-loaded differential amplifier to determine the common-mode gain.
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Figure 8.39 The active-loaded BJT differential pair suffers from a systematic input offset voltage resulting from the error in the currenttransfer ratio of the current mirror.
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Figure 8.40 An active-loaded bipolar differential amplifier employing a folded cascode stage (Q3 and Q4) and a Wilson current-mirror load
(Q5, Q6, and Q7).
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Figure 8.41 Two-stage CMOS op-amp configuration.
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Figure 8.42 Bias circuit for the CMOS op amp.
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Figure 8.43 A four-stage bipolar op amp.
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Figure 8.44 Circuit for Example 8.6.
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Figure 8.45 Equivalent circuit for calculating the gain of the input stage of the amplifier in Fig. 8.43.
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Figure 8.46 Equivalent circuit for calculating the gain of the second stage of the amplifier in Fig. 8.43.
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Figure 8.47 Equivalent circuit for evaluating the gain of the third stage in the amplifier circuit of Fig. 8.43.
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Figure 8.48 Equivalent circuit of the output stage of the amplifier circuit of Fig. 8.43.
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Figure 8.49 The circuit of the multistage amplifier of Fig. 8.43 prepared for small-signal analysis. Indicated are the signal currents throughout
the amplifier and the input resistances of the four stages.
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Figure P8.2
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Figure P8.6
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Figure P8.20
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Figure P8.21
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Figure P8.22
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Figure P8.23
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Figure P8.24
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Figure P8.25
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Figure P8.29
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Figure P8.54
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Figure P8.57
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Figure P8.59
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Figure P8.60
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Figure P8.61
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Figure P8.62
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Figure P8.63
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Figure P8.81
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Figure P8.87
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Figure P8.90
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Figure P8.98
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Figure P8.102
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Figure P8.104
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Figure P8.106
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Figure P8.108
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Figure P8.112
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Figure P8.118
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Figure P8.119
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Figure P8.120
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Figure P8.121
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