Little- and big-endian memory organizations bit 0 bit 31 bit 0 bit 31 23 22 21 20 20 21 22 23 19 18 17 16 16 17 18 19 word16 word16 14 15 13 12 12 10 11 9 8 8 6 5 4 byt e6 half -word4 2 3 1 byt e address 0 byt e3 byt e2 byt e1 byt e0 (a) Litt le-endian memory organizat ion ©2000 Addison Wesley 14 15 9 10 11 word8 word8 7 13 half -word12 half -word14 half -word14 half -word12 4 5 6 7 byt e5 half -word6 0 1 2 byt e address 3 byt e0 byt e1 byt e2 byt e3 (b) Big-endian memory organizat ion ARM operating modes and register usage. CPS R[ 4 : 0 ] 10000 10001 10010 10011 10111 11011 11111 ©2000 Addison Wesley Mo de User FIQ IRQ SVC Abort Undef System Us e Normal user code Processing fast interrupts Processing standard interrupts Processing software interrupts (SWIs) Processing memory faults Handling undefined instruction traps Running privileged operating system tasks Re g i s t e rs user _fiq _irq _svc _abt _und user Exception vector addresses Ex c e p t i o n Reset Undefined instruction Software interrupt (SWI) Prefetch abort (instruction fetch memory fault) Data abort (data access memory fault) IRQ (normal interrupt) FIQ (fast interrupt) ©2000 Addison Wesley Mo de SVC UND SVC Abort Abort IRQ FIQ Ve c t o r addre s s 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000018 0x0000001C The ARM condition code field 31 28 27 cond ©2000 Addison Wesley 0 ARM condition codes Op c o de [3 1 :2 8 ] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Mn e mo n i c ex tens i o n EQ NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL NV ©2000 Addison Wesley In t e rp re t at i o n Equal / equals zero Not equal Carry set / unsigned higher or same Carry clear / unsigned lower Minus / negative Plus / positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Signed greater than or equal Signed less than Signed greater than Signed less than or equal Always Never (do not use!) S t at us f l ag s t at e f o r e x e c ut i o n Z set Z clear C set C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N is not equal to V Z clear and N equals V Z set or N is not equal to V any none Branch and Branch with Link binary encoding 31 28 27 cond ©2000 Addison Wesley 25 2423 101 L 0 24-bit signed word of f set Branch (with optional link) and exchange instruction binary encoding (1) BX|BLX Rm 31 2827 6 5 4 3 0001001011111111111100 cond L 1 0 Rm (2) BLX label 31 2827 2524 23 1111 101 H ©2000 Addison Wesley 0 24-bit signed word offset Software interrupt binary encoding 31 28 27 cond ©2000 Addison Wesley 2423 1111 0 24-bit (interpret ed) immediat e Data processing instruction binary encoding 31 28 2726 25 24 cond 21 20 19 0 0 # opcode S 1615 Rn 12 11 0 operand 2 Rd destination register first operand register set condition codes arithmetic/logic function 25 11 8 7 #rot 1 0 8-bit immediate immediate alignment 11 7 6 5 4 3 #shift 25 immediate shift length 0 shift type Sh 0 0 Rm second operand register 11 8 7 6 5 4 3 Rs register shift length ©2000 Addison Wesley 0 Sh 1 0 Rm ARM data processing instructions Op c o de [2 4 :2 1 ] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Mn e mo n i c Me an i n g Ef f e c t AND EOR SUB RSB ADD ADC SBC RSC TST TEQ CMP CMN ORR MOV BIC MVN Logical bit-wise AND Logical bit-wise exclusive OR Subtract Reverse subtract Add Add with carry Subtract with carry Reverse subtract with carry Test Test equivalence Compare Compare negated Logical bit-wise OR Move Bit clear Move negated Rd := Rn AND Op2 Rd := Rn EOR Op2 Rd := Rn - Op2 Rd := Op2 - Rn Rd := Rn + Op2 Rd := Rn + Op2 + C Rd := Rn - Op2 + C - 1 Rd := Op2 - Rn + C - 1 Scc on Rn AND Op2 Scc on Rn EOR Op2 Scc on Rn - Op2 Scc on Rn + Op2 Rd := Rn OR Op2 Rd := Op2 Rd := Rn AND NOT Op2 Rd := NOT Op2 ©2000 Addison Wesley Multiply instruction binary encoding 31 28 27 cond ©2000 Addison Wesley 2423 0000 21 20 19 1615 12 11 mul S Rd/RdHi Rn/RdLo 8 7 Rs 4 3 1001 0 Rm Multiply instructions Op c o de [2 3 :2 1 ] 000 001 100 101 110 111 Mn e mo n i c Me an i n g Ef f e c t MUL MLA UMULL UMLAL SMULL SMLAL Multiply (32-bit result) Multiply-accumulate (32-bit result) Unsigned multiply long Unsigned multiply-accumulate long Signed multiply long Signed multiply-accumulate long Rd := (Rm * Rs) [31:0] Rd := (Rm * Rs + Rn) [31:0] RdHi:RdLo := Rm * Rs RdHi:RdLo += Rm * Rs RdHi:RdLo := Rm * Rs RdHi:RdLo += Rm * Rs ©2000 Addison Wesley Count leading zeros instruction binary encoding 31 28 27 cond 16 15 0 001 011 000 00 destination register ©2000 Addison Wesley 12 11 Rd 4 3 00 000 001 0 Rm source register Single word and unsigned byte data transfer instruction binary encoding 31 28 2726 25 2423 2221 20 19 cond 0 1 # P U BW L 1615 Rn 12 11 0 of f set Rd source/desti nation reg ister base r eg ister load/store write- back (auto- index) unsig ned byte/word up/down pre- /post-i ndex 25 11 12-bit immediat e 0 25 11 7 6 5 4 3 #shif t 1 immediate shift leng th shift type offset reg ister ©2000 Addison Wesley 0 Sh 0 0 Rm Half-word and signed byte data transfer instruction binary encoding 31 28 27 cond 25 2423 2221 20 19 000 PU#WL 1615 Rn 12 11 Rd 8 7 6 5 4 3 0 of f set H 1 S H 1 of f set L source/desti nation reg ister base r eg ister load/store write- back (auto- index) up/down pre- /post-i ndex 22 11 1 Imm [7:4] Imm [3:0] 22 11 3 8 0000 0 offset reg ister ©2000 Addison Wesley 8 3 0 0 Rm Data type encoding S 1 0 1 ©2000 Addison Wesley H 0 1 1 Dat a t y p e Signed byte Unsigned half-word Signed half-word Multiple register data transfer instruction binary encoding 31 28 27 cond 25 2423 2221 20 19 1 0 0 P U SW L 1615 Rn 0 register list base r eg ister load/store write- back (auto- index) restor e PSR and force user bi t up/down pre- /post-i ndex ©2000 Addison Wesley Swap memory and register instruction binary encoding 31 28 27 cond 23 2221 20 19 00010 B 00 1615 Rn 12 11 Rd 4 3 0000100 1 0 Rm destination r eg ister base r eg ister unsig ned byte/word ©2000 Addison Wesley source r eg ister Status register to general register transfer instruction binary encoding 31 28 27 cond 23 2221 1615 00010 R 001111 12 11 Rd 0 0000000 00000 destination r eg ister SPSR/CPSR ©2000 Addison Wesley Transfer to status register instruction binary encoding 31 28 27 26 25 24 23 22 21 20 19 cond 00 # 10 R 10 16 15 field 12 11 0 operand 1111 field mask SPSR/CPSR 25 11 1 8 7 #rot 0 8-bit immediate immediate alignment 25 11 0 00000000 operand register ©2000 Addison Wesley 4 3 0 Rm Coprocessor data processing instruction binary encoding 31 28 27 cond ©2000 Addison Wesley 2423 1110 20 19 Cop1 1615 CRn 12 11 CRd 8 7 CP# 5 4 3 Cop2 0 0 CRm Coprocessor data transfer instruction binary encoding 31 28 27 cond 25 2423 2221 20 19 1 1 0 P U NW L 1615 Rn 12 11 CRd 8 7 CP# 0 8-bit of f set source/desti nation reg ister base r eg ister load/store write- back (auto- index) data size ( copr ocessor dependent) up/down pre- /post-i ndex ©2000 Addison Wesley Coprocessor register transfer instruction binary encoding 31 28 27 cond 2423 21 20 19 1 1 1 0 Cop1 L 1615 CRn 12 11 Rd 8 7 CP# 5 4 3 Cop2 1 0 CRm load from coprocessor/store to coprocessor ©2000 Addison Wesley Breakpoint instruction binary encoding 31 28 27 111 0 ©2000 Addison Wesley 20 19 00 010 010 16 15 xxxx 12 11 x xx x 8 7 xxxx 4 3 01 11 0 xxxx Arithmetic instruction extension space 31 28 27 cond ©2000 Addison Wesley 2221 20 19 000001 op 1615 Rn 12 11 Rd 8 7 Rs 4 3 1001 0 Rm Control instruction extension space 31 28 27 23 2221 20 19 1615 12 11 8 7 6 c ond 0 0 0 1 0 op1 0 Rn Rd Rs c ond 0 0 0 1 0 op1 0 Rn Rd Rs c ond 0 0 1 1 0 op1 0 Rn Rd #rot ©2000 Addison Wesley op2 4 3 0 0 Rm 0 op2 1 Rm 8-bit immediate Data transfer instruction extension space 31 28 27 cond ©2000 Addison Wesley 25 2423 2221 20 19 0 0 0 P U BW L 1615 Rn 12 11 Rd 8 7 6 5 4 3 Rs 1 op1 1 0 Rm Coprocessor instruction extension space 31 28 27 cond ©2000 Addison Wesley 25 2423 2221 20 19 1 1 0 0 op 0 X 1615 Rn 12 11 CRd 8 7 CP# 0 of f set Undefined instruction space 31 28 27 cond ©2000 Addison Wesley 25 24 011 5 4 3 XXXXXXX XXXXXXXXXXXX X 0 1 XXXX Summary of ARM architectures Core Architecture ARM1 v1 ARM2 v2 ARM2as, ARM3 v2a ARM6, ARM600, ARM610 v3 ARM7, ARM700, ARM710 v3 ARM7TDMI, ARM710T, ARM720T, ARM740T v4T StrongARM, ARM8, ARM810 v4 ARM9TDMI, ARM920T, ARM940T v4T ARM9ES v5TE ARM10TDMI, ARM1020E v5TE ©2000 Addison Wesley