Every Wednesday:
15:00 hrs to 18:00 hrs
: عبرا ره
نيئات يڳو 6 ناک يڳو 3 ماش
DIGITAL INTEGRATED
CIRCUITS FOR
COMMUNICATION
يِڻاسرع دمحا ناسحا

My Introduction
فراعت وجنهنم
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

Ahsan Ahmad Ursani يڻاسرع دمحا ناسحا
Associate Professor رسيفورپ ٽيئيسوسيا
Dept. of Telecommunication
Engineering
تايطبر روڏ وبعش
TL-117 : ربمن رتفد
Office No: TL-117
زيجلاا نڪيٽ نشيڪينويمڪ ف ا ٽويٽيٽسنا
Institute of Communication
Technologies
Email:
Web page: ahsan.ursani@faculty.muet.edu.pk
https://sites.google.com/a/fac ulty.muet.edu.pk/aau/home
: لاپٽ قرب
: وحفص بيو
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The Teaching Plan
اٿر يسيردت
Pre-Requisite: IC Design
S. No. Chapter
1
2
3
Dynamc Combinational CMOS Logic
Designing Sequential Logic
Designing Memory and Array Structures
Total
Hours
10
17
21
48

The Textbook
باتڪ يباصن
Digital Integrated Circuits
A Design Perspective
Jan M. Rabaey
Chapter 6, 7, & 12

Chapter 2
نويرهپ باب
S. No.
Topic
1 Introduction
2
3
Static Latches and Registers
Dynamic Latches and Registers
6
7
8
4
5
9
10
Alternative Register Styles
Pipelining: An approach to optimize sequential
Speed and Power Dissipation
Non-Bistable Sequential Circuits
Perspective: Choosing a Clocking Strategy
Total
1
1
1
1
1
Hours
1
1
1
1
1
10

Timing Metrics for Sequential Circuits

Set-Up time t su

Time before clock transition

Hold time t hold

Time After clock transition
 worst-case propagation delay tc-q


 minimum delay (contamination delay) t cd
Propagation Delay of combinational logic t plogic
Time period of the Clock signal T

Timing Metrics for Sequential Circuits

Classification of Memory Elements

Foreground Memory
 embedded into logic
 organized as individual registers of register banks

Background Memory

Large amounts of centralized memory core

Not the subject of this chapter

Static

Not refreshed frequently

Circuits with Positive feedback

Multivibrators
Dynamic

Refreshed frequently

In order of miliseconds

Store state of parasitic capacitances of MOS

Higher performance

Lower Power
Dissipation


Level-sensitive circuit

Passes input D to the Output Q

Output does not change in the HOLD MODE

Input just before the going into HOLD phase is held stable during the following HOLD phase

An essential component of Edge-triggered Register


Basic Part of a memory

Having two stable states

Use +ve feedback

loop gain is greater than unity loop gain is much smaller than unity

Transition from one state to the other


This is generally done by applying a trigger pulse at Vi1 or Vi2
The width of the trigger pulse need be only a little larger than the total propagation delay around the circuit loop, which is twice the average propagation delay of the inverters

Using NAND Gates Using NOR Gates





Fully fully-complimentary
CMOS implementation of
SR flip Flop requires 8 transistors
Clocked operation will require extra transistors
Two Crossed Coupled
Inverters
4 extra transistors for R, S, and CLK inputs


M4, M7, and M8 forms a
ratioed Inverter

Q is high and R is applied
 we must succeed in bringing Q below the switching threshold of the inverter M1-M2

Must increase the size of
M5, M6, M7, and M8

Example 7.1: Transistor Sizing of
Clocked SR Latch







(W/L)
M1
= (W/L)
M3
= 0.5mm/0.25mm
(W/L)
M2
=(W/L)
M4
=1.5mm/0.25mm
V
M
= V
Q = 0
DD
/2
V
OL
(Q=0) < V
M
(W/L)
M5-6
≥ 2.26
(W/L)
M5
= (W/L)
M6
≥ 4.5

DC output voltage vs. individual pulldown device
Transient Response

Example 7.2: Propagation Delay of Static SR Flip-Flop

Problem 7.2 Complimentary CMOS SR FF

Instead of using the modified SR FF of Figure
7.8, it is also possible to use
complementary logic to implement the clocked SR FF.
Derive the transistor schematic (which consists of
12 transistors). This circuit is more complex, but switches faster and consumes less switching power. Explain why.

Advantages

The feedback loop is off while output is changing

Feedback is not to be overridden to change the output

Transistor sizing is not critical to fuctionality
Disadvantages

Clock load is 4

NMOS latch using Pass Transistors

Clock load = 2

Degraded logic 1 passed to the first inverter (V
DD
-V
TN
)

For smaller values of V
DD
 Less noise margin
 Less switching performance
 Static Power Dissipation

Master Slave Edge-triggered Register:
Positive edge-triggered

Problem 7.3: Optimization of the
Master Slave Register

I
1 and I
2 can be removed

Functionality affected ?

Timing properties of Multiplexer-based
Master-Slave Register

Set-up time

Hold time

Propagation Delay





Propagation Delay of
Inverter (t pd_inv
)
Propagation Delay of
Transmision Gate (t pd_tx
) t su t c-q
= 3 t pd_inv
= t pd_tx
+ t
(T
3
) pd_tx
+ t pd_inv t hold
= 0
(I
6
)

Master Slave Edge-triggered Register:
Negative Edge-trggerred

Draw a circuit based on transmission gate multiplexers


Progressively skew the input with respect to the clock edge until the circuit fails

Tsetup = 0.21 nsec Tsetup = 0.20 nsec


Tc-q = t pd_tx
(T
3
) + t pd_inv
(I
6
)



T c-q(LH)
T c-q(HL)
= 160 ps
= 180 ps


Feedback transmission gates removed

Clock load = 4

Ratioed Logic

T
1 should be properly sized so as to be able to change the I
1
I
2 state



T
2 can also drive T
1
I
4 must be a weak device to prevent it from driving T
2


Assumption that clock inversion takes ZERO time

Effects of Capacitive loads dissimilar capacitive loads due to different data stored in the connecting latches

Different routing conditions of the two signals

Clock Skew


Direct Path B/W D and Q

Race Condition

Can conduct on +ve edge of clock

Solution to Clock Skew: Pseudostatic
2-phase D register

Two phase Clock signal

2 non-overlaping phases



 t su
= t pinv t cq
= 2t pinv
+ t ptgate
Needs Refereshing

Clock Overlap can cause the problem called Race

1-1 Overlap

Increasing hold time

0-0 Overlap

T overlap0-0
< t
T1
+ t
I1
+ t
T2

Input Signal D must not be able to propagate through T overlap
2
During 0-0 o

C 2 MOS – Clocked CMOS
A Clock Skew Insensitive Approach

Positive Edge Triggered
Master –Slave Register

Clocked CMOS

CLK=0; Master samples the inverted version of D on X

CLK=1; Master is in the
HOLD mode and Slave passes the value on X to Q

0 – 0 Overlap

1 – 1 Overlap

2

0 – 0 overlap does not create any problem

1 – 1 overlap puts a HOLD constraint


It consists of two parallel masterslave based edge-triggered registers, whose outputs are multiplexed using
the tri-state drivers

The advantage of this scheme is that a lower frequency clock (half of the original rate) is distributed for the same functional throughput, resulting in power savings in the clock distribution network

True Single-Phase Clocked Register
(TSPCR)
Positive Latch Negative Latch

Example 7.4 Impact of embedding logic into latches on performance





Consider embedding an AND gate into the TSPC latch, as shown in Figure 7.31b. In a 0.25
mm, the set-up time of such a circuit using minimum- size devices is 140 psec. A conventional approach, composed of an AND gate followed by a positive latch has an effective set-up time of 600 psec (we treat the AND plus latch as a black box that performs both functions). The embedded logic approach hence results in significant performance improvements.

Simplified TSPC latch / Split Output

ADVANTAGES

Reduced
Implementaiton Area

Less Power
Consumption

Reduced Clock Load
DISADVANTAGES

All nodes do not experience full logic swing

Reduced Performance

This also limits the amount of VDD scaling possible on the latch


CLK = 0

Sampling inverted D on node X.

The second inverter is in the precharge mode

M6 charging up node
Y to VDD.

3 rd inverter is in HOLD,
M8 and M9 are off.

Positive Edge Triggered
Single-phase edge-triggered register


On the rising edge of the clock, the dynamic inverter M4-M6
evaluates. If X is high on the rising edge, node Y discharges.
The third inverter M7-
M8 is ON during the
high phase, and the node value on Y is passed to the output Q.

Positive Edge Triggered
Single-phase edge-triggered register





On the +ve phase of the clock, X transitions to a low if D transitions to a high level.
Input must be kept stable till the value on node X before the rising edge of the clock propagates to Y. This represents the hold time of the register
hold time less than 1 inverter delay since it takes 1 delay for the input to affect X.
The propagation delay of the register is 3 inverters since the value on node X must propagate to the output Q.
Finally, the set-up time is the time for node X
to be valid, which is 1 inverter delay.

TSPC Edge-Triggered Register
Transistor Sizing




D is low & X=Q~=1; Q=0.
CLK is low, Y is precharged high turning on M7.
CLK transitions from low to
high, Y and Q~ start dis- charging simultaneously
(through M4-M5 & M7-M8, respectively).
Once Y is sufficiently low, the trend on Q~ is reversed and the node is pulled high anew through M9.




 fatal errors, as it may create unwanted events
 when the output of the latch is used as a clock signal input to another register). It reduces the contamination delay of the register.
The problem can be corrected by
resizing the relative strengths of the pull-down paths through M4-M5 and
M7-M8, so that Y discharges much faster than Q.
This is accomplished by reducing the
strength of the M7-M8 pulldown path, and by speeding up the M4 -
M5 pulldown path.

TSPC Edge-Triggered Register
Transistor Sizing