Solving Op Amp Stability Issues
Part 2
(For Voltage Feedback Op Amps)
Tim Green & Collin Wells
Precision Analog Linear Applications
1
Stability
Tricks and Rules-of-Thumb
Loop Gain Bandwidth Rule: 45 degrees for f < fcl
Aolβ (Loop Gain) Phase Plot
180
fcl
90o
Phase Shift
at fcl
fp1
 (degrees)
135
Frequency
(Hz)
90
10
45o
“Phase Buffer”
away from
180o Phase Shift
45
0
-45
100
1k
fp2
10k
fz1
100k
1M
10M
90o
Phase Margin
at fcl
Loop Stability Criteria: < -180 degree phase shift at fcl
Design for: < -135 degree phase shift at all frequencies < fcl
Why?:
Because Aol is not always “Typical”
Power-up, Power-down, Power-transient  Undefined “Typical” Aol
Allows for phase shift due to real world Layout & Component Parasitics
Prevent excessive ringing due to phase margin dip near fcl
3
Frequency Decade Rules for Loop Gain
For 45O Phase Buffer away from 180O Phase Shift
fp1
fp1
fp2
fz1
fp3
Aol
pole
pole
---------
1/b
--------zero
pole
Loop Gain
pole
pole
pole
zero
100
Aol
A (dB)
80
Loop Gain View: Poles: fp1, fp2, fz1; Zero: fp3
Rules of Thumb for Good Loop Stability:
 Place fp3 within a decade of fz1
fp1 and fz1 = -135° phase shift at fz1
fp3 < decade will keep phase from dipping further
 Place fp3 at least a decade below fcl
Allows Aol curve to shift to the left by one decade
60
fcl
40
Rn
fp3
1/Beta
20
Cn
RF
fp2
fz1
+
0
VIN
1
10
100
1k
10k
100k
1M
10M
VOUT
RI
+
CL
-
Frequency (Hz)
VOUT/VIN
Note locations of poles in zeroes in Aol and 1/β plots
4
Frequency Decade Rules for Loop Gain
Phase Plot Prediction
Phase Shift (deg)
Phase Shift (deg)
Individual Pole & Zero Plot
+90
fp3
+45
0
fp1
-45
-90
fz1
1
10
fp1
fp2
fz1
fp3
+180
Aol
pole
pole
---------
100
1/b
--------zero
pole
Loop Gain
pole
pole
pole
zero
fp2
1K
10K
Frequency (Hz)
100K
1M
fcl
At fcl:
Phase Shift = 135O
Phase Margin = 45O
100K
1M
Final Plot
10M
+135
+90
+45
0
1
10
100
1K
10K
45O
Frequency (Hz)
“Phase Buffer”
Note locations of poles in zeroes in Aol and 1/β plots
10M
5
Op Amp Circuits & Second Order Systems
100
fp1
80
RI
RF
4.7k
4.7k
Aol
A (dB)
VOUT
60
+
+
VIN
40
-
1/Beta
fcl
20
fp2
0
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Most Op Amp Circuits are
adequately analyzed,
simulated, and real world
tested using well-known
second order system
response behavior.
Most Op Amps are dominated by Two Poles:
Aol curve shows a low frequency pole, fp1
Aol curve also has a high frequency pole, fp2
Often fp2 is at fcl for unity gain
This yields 45 degrees phase margin at unity gain
6
Control Loop - Second Order System
R(s)
G(s)
C(s)
2
C(s)
ωn
 2
R(s) s  2ωn s  ωn 2
w here:
ωn  naturalfre que ncy(rad/s )
ζ  dam pingratio
Clos e dLoopRe s pons e(Ste p and AC) :
Unde rdam ped : 0  ζ  1
M arginallyStable : ζ  0
CriticallyDam pe d: ζ  1
Ove rdam pe d: ζ  1
7
Closed Loop Peaking in
AC Frequency Sweep vs Phase Margin
Phase Margin
AC Peaking
@ wn
*
90°
-7dB
80°
-5dB
70°
-4dB
60°
-1dB
50°
+1dB
40°
+3dB
30°
+6dB
20°
+9dB
13°
+10dB
10°
+14dB
* Phase Margin:
1) Measure closed loop AC peaking in dB
2) Find dB peaking on graph above and read closest damping ratio, 
3) Use damping ratio, , to find phase margin using Slide 75 graph
8
From: Dorf, Richard C. Modern Control Systems. Addison-Wesley
Publishing Company. Reading, Massachusetts. Third Edition, 1981.
Transient Real World Stability Test
RI
RF
Volts
+VS
VOUT
VOUT
VOffset
-VS
VIN
1kHz
50mVPP
+
RL
IOUT
+
time
-
Test Tips:
 Choose test frequency << fcl
“Small Signal” AC Output Square Wave (1kHz usually works well)
 Adjust VIN amplitude to yield output <50mVpp
 Worst case is usually when VOffset = 0  Largest Op Amp RO (IOUT = 0)
 Use VOffset as desired to check all output operating points for stability
 Set scope = AC Couple & expand vertical scope scale to look for amount of
overshoot, undershoot, ringing on VOUT small signal square wave
 Use X1 Scope Probe on VOUT for best resolution
9
2nd Order Transient Curves
* 25%
*
Overshoot
(%)
10
15
20
25
30
35
40
45
50
Phase Margin
(deg)
57.5
50
42.5
40
35
32.5
30
27.5
25
* Phase Margin:
1) Measure closed loop transient overshoot (%)
2) Find overshoot on graph above and read closest damping ratio, 
3) Use damping ratio, , or Overshoot (%) to find phase margin using Slide 75 graph
10
From: Dorf, Richard C. Modern Control Systems. Addison-Wesley
Publishing Company. Reading, Massachusetts. Third Edition, 1981.
2nd Order Damping Ratio, Overshoot, Phase Margin
1.
2.
3.
4.
Overshoot = 40%, Phase Margin = 30 degrees
Start at % Overshoot on x-axis
Read up to “Damping Ratio” on “Percent Maximum Overshoot” curve
Read Across to Damping Ratio on y-axis
Use Damping Ratio to read across to “Phase Margin” curve.
Overshoot
(%)
10
15
20
25
30
35
40
45
50
 = 0.3
 = 0.3
fM = 30deg
Phase Margin
(deg)
57.5
50
42.5
40
35
32.5
30
27.5
25
40% = Overshoot
11
When RO is really ZO!!
OPA627 has RO
OPA2376 has ZO
Capacitive
Inductive
Resistive
OPA627
OPA2376
Resistive
Note: Some op amps have ZO characteristics other than pure
resistance – consult data sheet / manufacturer / SPICE Model
12
Open Loop Output Impedance – SPICE Measurement
SPICE Zo Te s t:
L1 1TH
Run SPICE AC Analys is
IG1 is AC Curre ntGe ne rator
IG1 DC Value  0A for unloade d Zo
Zo  Vout
Conve rt Vo
ut (dB) to Vout (Logarithmic)
Zout (ohm s ) Vout (Logarithmic)
Vee 15V
C1 1TF
-
+
Vout
+
Vcc 15V
T
IG1
U1 OPA627E
55.5
Ro (ohms)
55.0
54.5
54.0
53.5
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
100M
13
Summary for Stability
For Stability Loop Gain Analysis all we need is:
1)
2)
3)
4)
Aol – from op amp data sheet or macromodel
1/b – basic by application, modified for stability
Z_Load – given by application
Zo – Op Amp open loop, small signal AC output impedance
from op amp data sheet or macromodel
Stability General Comments:
1)
2)
3)
4)
5)
6)
7)
8)
Stability by modifying 1/b will decrease closed loop bandwidth
Stability compensation can slow large signal response (charging of caps) – check it
Simulate AC Transfer function (Closed Loop AC Response) as final check
Simulate Small Signal Transient Response as final check
DC operation in the lab does not guarantee stability
Marginal stability can cause undesired overshoot and ringing
DC circuits can get real world transient inputs from supplies, inputs, or output
That ringing in your circuit is not your Grandmother’s dial telephone
T

64.94m
VOUT
33.64m
100u
150u
200u
Time (s)
250u
300u
14
Acknowledgements
A special thanks to Jerald Graeme, whom we honorably dub “The Godfather of
1/b” for his work at Burr-Brown Corporation in research and writing about
Op Amp Stability using 1/b.
Jerald Graeme Brief Biography:
From: http://electronicdesign.com/analog/jerald-graeme
When ICs and op amps were separate devices, Jerald Graeme was among the first to develop a combined IC
op amp while at Burr-Brown, in a 1968 team effort with Motorola. He designed many more op amps and video
amplifiers whose precision, high speed, or low drift amplification made them a very useful component in a
variety of analog applications. Nine U.S. patents and numerous foreign counterparts resulted from these
designs. The internationally acknowledged authority on electronic amplifiers wrote five very popular books about
op amps, the latest being Photodiode Amplifiers: Op Amp Solutions and Optimizing Op Amp Performance. The
latter, subtitled "A new approach for maximizing op amp behavior in circuit designs without extensive
mathematical analysis," offers design equations and models that reflect real-world op amp behavior and makes
analysis of difficult-looking configurations easy. Graeme's earlier books are: Op Amps: Design and Application,
Designing with Operational Amplifiers, and Amplifier Applications of Op Amps. He expects signal processing
with op amps to be the domain of digital devices, but they will still require an analog interface to integrate with
real-world items like process control or avionics.
Jerald Graeme Books:
http://www.amazon.com/Jerald-G.-Graeme/e/B001HO9X60
15
Acknowledgements
Op Amp Stability Series
Tim Green, Senior Analog Applications Engineer
Texas Instruments
http://www.engenius.net/site/zones/acquisitionZONE/technical_notes/acqt_050712
16
Appendix
17
Appendix Index
1) Op Amp Output Impedance
2) Pole and Zero: Magnitude and Phase on Bode Plots
3) Dual Feedback Paths and 1/b
4) Non-Loop Stability Problems
5) Stability: Riso (Output Cload)
6) Stability: High Gain and CF (Output Cload)
7) Stability: CF Non-Inverting (Input Cload)
8) Stability: CF Inverting (Input Cload)
9) Stability: Noise Gain Inverting & Non-Inverting (Output Cload)
10) Stability: Noise Gain and CF (Output Cload)
11) Stability: Output Pin Compensation (Output Cload)
12) Stability: Riso w/Dual Feedback (Output Cload)
– Zo, 1/b, Aol Technique
13) Stability: Discrete Difference Amplifier (Output Cload)
18
Appendix Index
Appendix No.
Title
1
Op Amp Output Impedance
Pole and Zero:
2
Magnitude and Phase on Bode Plots
3
Dual Feedback Paths and 1/β
4
Non-Loop Stability Problems
Description/Stability Technique
Zo vs Zout difference and datasheet curves
Closed loop magnitude and phase shifts of a signal
frequency due to poles and zeroes on a Bode Plot
How to avoid problems when using dual feedback
paths for stability compensation
Oscillations and causes not seen in loop gain stability
simulations
When to use the Stability Technique
Zo is a key parameter for stability analysis
Magnitude and phase shift at a frequency of
interest for closed loop poles and zeroes
Key tool in analyzing op amp circuits that use
dual feedback for stability
Check all designs to avoid oscillations that do
not show up in SPICE simulation
Output Cload, Note: accuracy of output is
dependent upon load current
5
Riso (Output Cload)
Stability: Isolation resistor with feedback at op amp
6
High Gain and CF (Output Cload)
Stability : High gain circuits and a feedback capacitor
7
CF Non-Inverting (Input Cload)
Stability : Non-inverting gain and feedback capacitor
Output Cload, closed loop gain >20dB
Input Cload, non-inverting gain, large value
input resistor
8
Stability: Inverting gain and feedback capacitor
Input Cload, non-inverting gain, large value
input resistor, photodiode type circuits
9
CF Inverting (Input Cload)
Noise Gain Inverting and
Non-Inverting (Output Cload)
10
Noise Gain and CF (Output Cload)
Stability: Noise Gain added by input R-C network
Stability: Noise Gain (input R-C) and feedback
capacitor
11
12
Output Pin Compensation (Output Cload)
Riso w/Dual Feedback (Output Cload)
- Zo, 1/β, Aol Technique
Stability: Series R-C on op amp output to ground
Stability: Isolation resistor with two feedback paths analysis by Zo, 1/β, and Aol technique
13
Discrete Difference Amplifier (Output Cload)
Stability: Balanced use of noise gain (series R-C)
Output Cload, closed loop gain <20dB
Output Cload, Loaded Aol has a second pole
located >20dB
Output Cload, no access to -input, monolithic,
integrated difference amplifiers, complex
feedback where not practical to use -input
Output Cload, some additional Vdrop across
isolation resistor is okay, accurate Vout at load
Output Cload, difference amp configuration,
any closed loop gain
19
1) Op Amp Output Impedance
Open Loop (ZO)
&
Closed Loop (ZOUT)
Op Amps and “Output Resistance”
Definition of Terms:
RO = Op Amp Open Loop Output Resistance
ROUT = Op Amp Closed Loop Output Resistance
RF
RI
RO
-IN
RDIFF
VFB
xAol
+
VE
VOUT
VO
IOUT
-
1A
+
+IN
Op Amp Model
ROUT = RO / (1+Aolβ)
ROUT = VOUT/IOUT
21
From: Frederiksen, Thomas M. Intuitive Operational Amplifiers.
McGraw-Hill Book Company. New York. Revised Edition. 1988.
Derivation of ROUT
(Closed Loop Output Resistance)
1) b = VFB / VOUT = [VOUT (RI / {RF + RI})]/VOUT = RI / (RF + RI)
2) ROUT = VOUT / IOUT
3) VO = -VE Aol
4) VE = VOUT [RI / (RF + RI)]
5) VOUT = VO + IOUTRO
6) VOUT = -VEAol + IOUTRO Substitute 3) into 5) for VO
7) VOUT = -VOUT [RI/(RF + RI)] Aol+ IOUTRO Substitute 4) into 6) for VE
8) VOUT + VOUT [RI/(RF + RI)] Aol = IOUTRO Rearrange 7) to get VOUT terms on left
9) VOUT = IOUTRO / {1+[RIAol/(RF+RI)]} Divide in 8) to get VOUT on left
10) ROUT = VOUT/IOUT =[ IOUTRO / {1+[RIAol / (RF+RI)]} ] / IOUT
Divide both sides of 9) by IOUT to get ROUT [from 2)] on left
11) ROUT = RO / (1+Aolβ) Substitute 1) into 10)
ROUT = RO / (1+Aolβ)
22
ROUT vs RO
RO does NOT change when Closed Loop feedback
is used
ROUT is the effect of RO, Aol, and β controlling VO
 Closed Loop feedback (β) forces VO to increase or
decrease as needed to accommodate VO loading
 Closed Loop (β) increase or decrease in VO appears at
VOUT as a reduction in RO
 ROUT increases as Loop Gain (Aolβ) decreases
23
When RO is really ZO!!
OPA627 has RO
OPA2376 has ZO
Capacitive
Inductive
Resistive
OPA627
OPA2376
Resistive
Note: Some op amps have ZO characteristics other than pure
resistance – consult data sheet / manufacturer
24
With Complex ZO, Accurate Models are Key!
L1 1TH
SPICE Te s tof Op Am pM acro Zo :
V2 2.5V
C1 1TF
4
3
2
-
Vout
+
+
1
5
U1 OPA2376
V1 2.5V
T
IG1 0
Run SPICE AC Analys is
IG1 is AC Curre ntGe ne rator
IG1 DC Value  0A for unloade d Zo
Zo  Vout
Conve rt Vout (dB) to Vout (Logarithmic)
Zout (ohm s ) Vout (Logarithmic)
1.00k
Impedance (ohms)
OPA2376
100.00
10.00
400uA Load
1.00
100.00m
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
25
Some Data Sheets Specify ZOUT NOT ZO
Recognize ROUT instead of RO:
ROUT inversely proportional to Aol
ROUT typically <100 at high frequency
ROUT is Inve rs eof Aol :
RO
1  Aolb
1

Aol
ROUT 
ROUT
This is really
ZOUT or ROUT!
TLC082
1
TLC082
3
2
2
3
1
26
Some Data Sheets Specify ZOUT NOT ZO
Point frequency Aol
---------(Hz)
(dB)
1
10M
0
2
100k
40
3
10k
60
ROUT (AV=1)
Datasheet
(ohms)
100
2
0.2
ROUT (AV=1)
Computed
(ohms)
RO = 200
2
0.2
TLC082
Com puteR O fromR OUT w hereAolb  1 (0dB) :
1
2
R OUT  100Ω for A V  1, f  10MHz, Aolb  1 (0dB)
RO
1  Aolβ
R
100  O  RO  200
1 1
ROUT 
3
27
2) Pole and Zero:
Magnitude & Phase on Bode Plots
28
Formulae for Pole and Zero Calculations
Ze roM agnitudefor f
w he re:
Pole M agnitudefor f
w he re:
f  fre que ncyof s ignal
f  fre que ncyof s ignal
fz  fre que ncyof pole
fp  fre que ncyof pole
Magnitude( dB)  20  LOG10
Pole Phase Shift for f
w here:
f  frequencyof signal
fp  frequencyof pole
Phase( deg )   tan1(
f
)
fp
1
f2
1 2
fp
Magnitude( dB)  20  LOG10 1 
f2
fz2
Ze roPhas e Shift for f
w he re:
f  fre que ncyof s ignal
fz  fre que ncyof pole
f
Phase( deg )   tan1( )
fz
29
Closed Loop Gain: Magnitude and Phase
Clos e dLoopM agnitudeand Phas e for fre que ncyf :
w he re:
f  fre que ncyof s ignal
fp1  fre que ncyof pole 1
fp2  fre que ncyof pole 2
fz1 fre que ncyof ze ro1
fz2  fre que ncyof ze ro2
K  DC Gain in V/V
Magnitude( dB)  20  LOG10 K  20  LOG10
Phase(deg)   tan1(
1
1
f2
f2
 20  LOG10
 20  LOG10 1  2  20  LOG10 1 
f2
f2
f z1
f z22
1
1

f p12
f p22
f
f
f
f
)  tan1(
)  tan1( )  tan1( )
f p1
f p2
f z1
f z1
30
Closed Loop Gain: Magnitude and Phase
1
1

 10.00974485Hz
2  R1 C1 2  1k  15.9F
1
1
fp2 

 1.004766055kHz
2  RF  CF 299k  1.6nF
fp1 
CF 1.6nF
RF 99kOhm
V2 2.5V
RI 1kOhm
U1 OPA364
Clos e dLoop M agnitudeand Phas e for fre que ncyf :
+
+
VOUT
+
w he re:
f  fre que ncyof s ignal
R1 1kOhm
VIN
V1 2.5V
fp1  fre que ncyof pole 1
fp2  fre que ncyof pole 2
C1 15.9uF
K  DC Gain in V/V
Magnitude( dB)  20  LOG10 K  20  LOG10
Phase(deg)   tan1(
1
1
 20  LOG10
2
f
f2
1
1

fp12
fp22
f
f
)  tan1(
)
fp1
fp2
Magnitude( dB)  20  LOG10 (100)  20  LOG10
Phase(deg)   tan1(
1
1
 20  LOG10
2
f
f2
1
1

(10.00974485)2
(1.004766055e3)2
f
f
)  tan1(
)
10.00974485
1.004766055e3
31
Closed Loop Gain: Magnitude and Phase
T
40
20
[B]
Gain :
0
VOUT B:(3.924588k; -24.084018)
[A]
Gain (dB)
-20
Phase :
VOUT B:(3.924588k; -163.475026)
Gain :
-40
VOUT A:(92.20173; 20.624635)
Phase :
-60
VOUT A:(92.20173; -89.067371)
-80
-100
-120
-140
0.00
Phase [deg]
-45.00
-90.00
-135.00
-180.00
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
32
Spice Compared with Calculated Analysis
SPICE AC Analysis:
For best accuracy use highest resolution
i.e. maximum “Number of Points”
f
(Hz)
---------9.22017300E+01
3.92458800E+03
Magnitude
(dB)
Calculated
20.6263744
-23.97775119
Magnitude
(dB)
SPICE
20.624635
-24.084018
Phase
(deg)
Calculated
-89.04706182
-165.49354967
Phase
(deg)
SPICE
-89.067371
-163.475026
Note:
1) SPICE analysis accounts for loop gain effects and closed loop phase shifts
due to op amp Aol.
2) Calculated results do not account for loop gain effects and closed loop phase shifts
due to op amp Aol.
33
Closed Loop Gain: Magnitude and Phase
SPICE Ideal Op Amp & Poles: Equivalent Circuit
DC Gain 100
VG1
f
(Hz)
---------9.22017300E+01
3.92458800E+03
Buffer 1
RF 99kOhm
+
R1 1kOhm
C1 15.9uF
+
+
-
-
Magnitude
(dB)
Calculated
20.6263744
-23.97775119
Magnitude
(dB)
SPICE - Ideal
20.626374
-23.977751
CF 1.6nF
+
+
-
-
Phase
(deg)
Calculated
-89.04706182
-165.49354967
VOUT
Phase
(deg)
SPICE - Ideal
-89.047062
-165.49355
Note:
1) SPICE - Ideal Circuit analysis matches Calculated results.
2) No loop gain effect or closed loop phase shifts due to op amp Aol.
34
Closed Loop Gain: Magnitude and Phase
SPICE Ideal Op Amp & Poles: Equivalent Circuit
T
40
20
[B]
0
Gain (dB)
SPICE Poles-Magnitude and Phase
Ideal Op Amp Circuit
[A]
-20
Gain :
-40
VOUT A:(92.20173; 20.626374)
-60
Phase :
VOUT A:(92.20173; -89.047062)
-80
Gain :
-100
VOUT B:(3.924588k; -23.977751)
-120
Phase :
-140
VOUT B:(3.924588k; -165.49355)
-160
0
Phase [deg]
-45
-90
-135
-180
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
35
3) Dual Feedback Paths and 1/b
36
Dual Feedback and 1/β Concept
FB#1
RF
Analogy: Two people are talking in your ear. Which
one do you hear? The one talking the loudest!
CF
FB#2
RI
-
VO RO
VOA
+
VIN
VOUT
Riso
CL
Dual Feedback: Op amp has two feedback paths
talking to it. It listens to the one that feeds back the
largest voltage (β = VFB / VOUT). This implies the
smallest 1/β!
+
-
100
Dual Feedback Networks:
Analyze & Plot each FB#? 1/β
80
A (dB)
Aol
 Smallest FB#? dominates 1/β
60
 1/β = 1 / (β1 + β2)
FB#1
b
FB#2
b
40
 1/β relative to VO
Note: VO = Op Amp Aol Output before
Ro for this Dual Feedback Example
1/Beta
[1/(b1 + b2)]
20
0
1
10
100
1k
10k
Frequency (Hz)
100k
fcl
1M
10M
37
Dual Feedback and 1/β
How will the two feedbacks combine?
Large b
Answer:
Small 1/β
The Largest β
(Smallest 1/β) will
dominate!
Small b
Large 1/β
-
38
Dual Feedback and the BIG NOT
WARNING: This can be
hazardous to your circuit!
100
Aol
80
A (dB)
FB#1
1/Beta
60
FB#2
40
1/Beta
20
0
1
10
100
1k
10k
100k
fcl
1M
10M
Frequency (Hz)
Dual Feedback and the BIG NOT:
1/β Slope changes from +20db/decade to -20dB/decade





Implies a “complex conjugate pole ” in the 1/β Plot with small damping ratio, ζ.
Implies a “complex conjugate zero” in the Aolβ (Loop Gain Plot) with small damping ratio, ζ.
+/-90° phase shift at frequency of complex zero/complex pole.
Phase slope from +/-90°/decade slope to +/-180° in narrow band near frequency
of complex zero/complex pole depending upon damping ratio, ζ.
Complex zero/complex pole can cause severe gain peaking in closed loop response.
39
Complex Conjugate Pole Phase Example
From: Dorf, Richard C. Modern Control Systems. Addison-Wesley Publishing Company. Reading, Massachusetts.
Third Edition, 1981.
40
Dual Feedback and 1/β Example
RF 100k
CF 82n
FB#1
FB#2
VEE 12
VO 5V
-
U2 REF02
U1 OPA177E
Vin
Gnd
REF02
+
Trim
Riso 26.7
Vout
5V
+
Out
CL 10u
VREF 5V
VCC 12
Dual Feedback:
FB#1 through RF forces accurate Vout across CL
FB#2 through CF dominates at high frequency for stability
Riso provides isolation between FB#1 and FB#2
41
Zo External Model for Dual Feedback Analysis
RF 100k
CF 82n
VFB 4.999V
VEE 12
-
U2 REF02
U1 OPA177E
Vin
Gnd
REF02
+
Trim
+
Z o External Model
VOA 4.9991V
VCV1
Ro 60
x1
+
+
Out
-
-
VO 4.9991V
Vout
Riso 26.7
4.9991V
CL 10u
VREF 4.999V
VCC 12
Zo External Model:
VCV1 ideally isolates U1 so U1 only provides data sheet Aol
Set Ro to match measured Ro
Analyze with unloaded Ro (largest Ro) which creates worst instability
Use 1/β on Aol stability analysis
1/β, taken from VOA will include the effects of Zo, Riso and CL
42
Dual Feedback, FB#1 And FB#2
RF 100k
CF 82n
VFB 4.999V
FB#2
VEE 12
-
U2 REF02
U1 OPA177E
Vin
Gnd
REF02
+
Trim
+
Z o External Model
VOA 4.9991V
VCV1
Ro 60
x1
+
+
Out
FB#1
-
-
VO 4.9991V
Vout
Riso 26.7
4.9991V
CL 10u
VREF 4.999V
VCC 12
FB#1 and FB#2 1/ β Analysis:
There is only one net voltage fed back as β to the -input of the op amp
β_net = β_FB#1 + β_FB#2
This implies that the largest β will dominate → smallest 1/ β will dominate
Analyze FB#1 with CF = open since it will only dominate at high frequencies
Analyze FB#2 with CL = short since it is at least 10x CF
43
Dual Feedback and 1/β Example
T
160
140
Aol
120
100
FB#1 1/b
Gain (dB)
80
60
1/b FB#2
FB#1
fcl
40
20
fza
fpc
1/b
0
fzx
-20
Vout/Vin
-40
10m
100m
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
44
Dual Feedback and 1/β – Create the BIG NOT
VFB 4.999V
LT 1T
Aol = VOA
FB#1: 1/Beta1= VOA / VF B
Loop Gain = VFB
RF 100k
+
CT 1T
VG1
CF 220p
VEE 12
Vtrim 1.2298V
-
U2 REF02
U1 OPA177E
Vin
Gnd
REF02
+
Trim
+
Zo External Model
VOA 4.9991V
Ro 60
VCV1
x1
+
+
Out
-
-
VO 4.9991V
Riso 26.7
Vout
4.9991V
CL 10u
VREF 4.999V
VCC 12
45
Dual Feedback and 1/β – Create the BIG NOT
T
160
140
Aol
120
100
FB#1 1/b
Gain (dB)
80
60
1/b FB#2
FB#1
40
fcl
20
fpc
fza
0
1/b
-20
-40
10m
100m
1
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
46
Dual Feedback and 1/β – Create the BIG NOT
T
160
140
Aol
120
100
???
STABLE
???
Gain (dB)
80
60
fcl
BIG
NOT
40
20
BIG NOT 1/
0
-20
-40
10m
100m
1
10
100
1k
Frequency (Hz)
10k
100k
1M
BIG NOT 1/b: At fcl rate-of-closure rule-of-thumb says circuit is stable but is it?
10M
47
Dual Feedback and 1/β – Create the BIG NOT
???
STABLE
???
BIG NOT Loop Gain:
Loop Gain phase shift >135 degrees (<45 degrees from 180 degree phase shift) for
frequencies <fcl which violates the loop gain phase buffer rule-of-thumb. But is it stable?
48
Dual Feedback and 1/β – Create the BIG NOT
VFB 4.999V
DC=0V
Trans ient=10mVpp
f =100Hz, 10ns rise/f all
CF 220p
VEE 12
Vtrim 1.2298V
-
U2 REF02
Vin
Vin
Gnd
REF02
Trim
Out
RF 100k
+
+
+
Zo External Model
VOA 4.9991V
VCV1
Ro 60
x1
+
+
U1 OPA177E
-
-
VO 4.9991V
Riso 26.7
Vout
4.9991V
CL 10u
VREF 4.999V
VCC 12
49
Dual Feedback and 1/β – Create the BIG NOT
T
5.38
VO
4.34
6.10
VOA
3.04
100.00m
Vin
-100.00m
5.17
STABLE
Vout
4.76
0.00
2.50m
5.00m
Time (s)
7.50m
10.00m
BIG NOT Transient Stability Test:
Excessive ringing and marginal stability are apparent. Real world implementation and
use may cause even more severe oscillations. We do not want this in production!
50
4) Non-Loop Stability Problems
Non-Loop Stability
• Loop Frequencies
• RB+
• PCB Traces
• Supply Bypass
• Ground Loops
• Output Stage Oscillations
Non-Loop Stability
Oscillations NOT predicted by Loop Gain (Aolb) Analysis
or
SPICE Simulations
52
Non-Loop Stability: Loop Frequency Definitions
fcl:
Where Loop Gain (Aolβ) = 1
Aol
100
fGBW:
Where Op Amp Aol Curve crosses 0dB
(Unity Gain Bandwidth)
A (dB)
80
fGBW
fcl
60
b
40
VOUT/VIN
20
SSBW
(Small Signal BandWidth)
0
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
53
Non-Loop Stability: ? Diagnostic Questions ?
 Frequency of oscillation (fosc)?
 When does the oscillation occur?
 Oscillates Unloaded?
 Oscillates with VIN=0?
54
Non-Loop Stability:
RB+ Resistor
 fosc < fGBW
 oscillates unloaded? -- may or may not
 oscillates with VIN=0? -- may or may not
RF
100k
RI
100k
RB+ is Ib current match resistor to
reduce Vos errors due to Ib.
Ib
-
+
VIN
-
VOUT
Ib
+
RB+
49.9k
RB+ can create high impedance
node acting as antenna pickup for
unwanted positive feedback.
+
VNOISE
PROBLEM
RF
-
100k
RI
100k
RF
-
100k
SOLUTION
RI
100k
VOUT
+
VIN
-
+
RB+
49.9k
CB+
0.01F
or
0.1F
If you use RB+ bypass
it in parallel with 0.1μF
capacitor.
+
VIN
-
-
VOUT
+
RB+
SOLUTION
Many Op Amps have low Ib so error is
small. Evaluate DC errors w/o RB+.
55
Non-Loop Stability:
PCB Traces
 fosc < fGBW
 oscillates unloaded? -- may or may not
 oscillates with VIN=0? -- may or may not
RI
RF
+
+
Rs
VIN
-
VOUT
GND
DO NOT route high current, low impedance output traces near high
impedance input traces. Unwanted positive feedback path.
DO route high current output traces adjacent to each other (on top of each
other in a multi-layer PCB) to form a twisted pair for EMI cancellation.
56
Non-Loop Stability:
Supply Lines
 fosc < fGBW
 oscillates unloaded? -- no
 oscillates with VIN=0? -- may or may not
Ls
PROBLEM
Gain
Stage
PROBLEM
Power
Stage
+vs
RL
IL
-
Rs
+
CL
-vs
Load current, IL, flows through power
supply resistance, Rs, due to PCB trace
or wiring. Modulated supply voltages
appear at Op Amp Power pins.
Modulated signal couples into amplifier
which relies on supply pins as AC
Ground.
Power supply lead inductance, Ls,
interacts with a capacitive load,
CL, to form an oscillatory LC, high
Q, tank circuit.
57
Non-Loop Stability:
Proper Supply Line Decouple
CLF
SOLUTION
CLF: Low Frequency Bypass
< 4 in
<10 cm
RHF
10μF / Amp Out (peak)
Aluminum Electrolytic or Tantalum
CHF
+VS
< 4 in (10cm) from Op Amp
-
CHF: High Frequency Bypass
+
0.1μF Ceramic
-VS
< 4 in
<10 cm
Directly at Op Amp Power Supply Pins
CHF
RHF
RHF: Provisional Series CHF Resistance
1Ω < RHF < 10Ω
CLF
Highly Inductive Supply Lines
58
Non-Loop Stability:
Ground Loops
RI
 fosc < fGBW
 oscillates unloaded? -- no
 oscillates with VIN=0? -- yes
RI
RF
RF
+
-
-
+VS
VOUT
VIN
+
-VS
-
RGw
RL
IL
RGx
+
RGy
“Ground”
Ground loops are created from load current
flowing through parasitic resistances. If part
of VOUT is fed back to Op Amp +input,
positive feedback and oscillations can occur.
SOLUTION
VIN
PROBLEM
RGv
“Star”
Ground
Point
-
+VS
VOUT
+
-VS
RL
RG
Parasitic resistances can be made to look
like a common mode input by using a
“Single-Point” or “Star” ground connection.
59
Non-Loop Stability:
Output Stages
 fosc > fGBW
 oscillates unloaded? -- no
 oscillates with VIN=0? -- no
RF
100k
L
O
A
D
RI
100k
+
VIN
VOUT
+
RSN
10 to 100
-
CSN
.F to 1F
-VS
PROBLEM
Some Op Amps use composite output
stages, usually on the negative output, that
contain local feedback paths. Under reactive
loads these output stages can oscillate.
SOLUTION
The Output R-C Snubber Network lowers
the high frequency gain of the output stage
preventing unwanted oscillations under
reactive loads.
60