Integration Challenges in Single-Chip Radios
Adil Kidwai
Intel Corporation, Hillsboro
Outline
• Motivation – product targets
• Architecture overview – Single-chip WiFi
• Issues and Mitigation Techniques
• Multi-standard coexistence in Single-chip
• Issues and Mitigation techniques
• Conclusions
ASP
Integration
Why Integrate?
Cost Pressure  Innovation
Double Sided Solution
More
Functionality
$
BOM
Time
Need to push the BOM down
Multi-Comm
ASP = Average Sales Price
BOM = Bill of Material (Cost)
Why not to integrate?
• Technology
– It places extra dependence on RF design
– To get to single-chip, the RF must migrate
technologies at same pace as digital flow
• Sku variation
– How easy will it be to create different die for
different markets and applications?
– Multi-com becomes more complex to make
silicon changes
Single chip defined (or not)
Antennas
FEM
FEM
RFIC
RFIC
MAC
MAC
• What is single-chip?
– If you have a FEM, is it still single-chip?
– How many devices should be combined to achieve the goal?
What is the Goal?
Integration and Single-chip
dc-dc
LVR
LVR
LVR
Ant 1
Analog
interface
FEM
Radio
Ant 2
MAC/PHY
Digital
interface
FEM
Ref clock
VCO
Xtal
EEPROM
Specific Example
Single-chip WiFi – Top Down Design
• Start with final
board target
• Determine
expected BOM
• Dive into package
• Only then, into the
silicon
J.C.Jensen, A.A. Kidwai et al. RFIC 2010
Issues in single-chip radios
• Package coupling
• Board coupling
• Silicon coupling
• Thermal issues
Package Modeling
• Modeling is important
part of predicting,
understanding, and
mitigating package
impacts
QFN and flip chip technologies
presented here
Pin placement
• Generic
wirebond
• Dual row
• Depopulated
inner row
• Frame,
bondwires,
paddle, … all
couple signals
• Placement is key
The Periphery
• The periphery design (pads, ESD and IO
driver cells) is integral to the design of
single chip products
• IOs drive signals off chip… or around the
chip to sensitive circuits
ESD
Isolation
Silicon Floor plan
vco
PA
dc2dc
PCIe
• The IO periphery
was cut into two
separate domains
• Local subsectors
exist for further
separation
• Distance is #1
factor for isolation
• Main aggressors
are placed as far
apart as possible
Isolation basics
• Taps typically reduce coupling by 20-30dB
• Deep nwell can double that if used appropriately
– Appropriately means separate and quiet ground (see
next slide)
epi
RX
tap
Large tap
substrate
tap
TX
Silicon Technology
• Deep nwell must be tied to quiet supply and
usually they are hard to come by
• Must provide a very low impedance path to that
ground
Clean ground A
nwell tap
n+
gate
p+
n+
iso-pw
gateClean ground B
source iso-pwell tap
n+
p+
n+
iso-pwell
drain
n+
Any old
drain
supply
n+
p+
deep nwell
p+
drain
p+
n+
psub
substrate
gate
Iso-pwell to nwell diode
n+
n+
p+
iso-pw
Lossy substrate
dnw
dnw
nwell
to psub diode
Power Delivery and isolation
IO power
First step to
protecting circuits
is to isolate power
domains
Isolation between
supplies depends
on:
– Regulator PSRR
– Board decoupling
methods
VCO
CP
Pres
buffer
LOG
RX RF
TX
RF Domain
XO
Synthesizer
RF
dc2dc
Digital
dc2dc
Analog
Digital
Host
PLL
ADC/
DAC
Bias
BG
Power Delivery and Isolation
Vssp
Vcc_core1 Vcc_phy
Vss
Vss
Vccp
Vcc3
Vccp
Domain2
Vssp
Vss
VDDOD
Vss
Vss
Vssp
Vcc2
Vccp
Vssp
Vcc IO
Vccp
Vssp
`
Vss
Vccp
Vss
Vcc1
Vcc5
Domain 3
Vssp
Domain1
Analog
Vcc4
Vss
• Generally…
what works
for ESD
performance,
increases the
potential for
coupling
signals
Vcc_IO
Vccp
Vss
Vccp
Vssp
Vcc4
Vcc
Vcc_core
Board coupling issue: Example
Aggressor
Victim
Aggressor
Victim
Aggressor
Victim
PMU noise coupling issue: Example
• Noise from the on-chip
dc-dc is well below spec
for on soldered parts; but
can be seen in ADC SNR
(through power supply) in
socketed parts
• The ground connection
for a the package will
affect the impact of the
dc-dc on circuits and the
ability to couple to other
parts of the product
Ant 1
Ant 1
LVR
LVR ADC
Radio
dc-dc
supply
MAC/PHY
Host
LVR
Xtal
EEPROM
DC-DC impact on receiver performance
Thermal issues in single-chip: Example
DC-DC
• Overall dissipation may
remain unchanged; but
the thermal density
increases
• This is one of the biggest
limitations in integrating
products
• Concurrent mode
operation of multi-com
products becomes
challenging
Power
Amplifier
PCIe
Spurs in single-chip: Example
• 40MHz spurs from
the charge pump
travel from loop
filter into RX on
board by
proximity
• Board and pin
location issue, not
chip or package
issue
LVR
LVR
LVR
dc-dc
supply
LVR
LF
LF
Ant 1
FEM
Radio
MAC/PHY
Radio
AntAnt11
Host
FEM
FEM
Xtal
EEPROM
WiFi-BT coupling: Example
Balun
Balun
iTR
SP3T
Chain A
RX / TX
WiFi
BT
(leaked to WiFi port)
Mirror
(2BT – WiFi)
WiFi
1x2 RFIC
Chain B
RX only
BT chain
RX / TX
BT
WiFi Transmitter Chain
WiFi-BT coupling: Example continued
Q
I BB
45o
VDD
Pre-Driver
Driver
Power
Amplifier
I
Q BB
VSS
2*BT couples to the
driver ground
With default pre-driver current
(18mA)
With default pre-driver current
(31mA)
Linearize the pre-driver device by degeneration
Coupling through Internal Switch
Second Harmonic
Balun
Balun
Balun
Balun
External switch
iTR
SP3T
iTR
Internal switch
6-7dB better performance:
Internal switch solution is
differential
Chain A
RX / TX
WiFi
1x2 RFIC
Chain B
RX only
BT chain
RX / TX
BT
Specifications achieved for WiFi single-chip
This Work
(measured at the antenna
connector)
Standard
802.11b/g/n
S. Khorram et al. JSSC-05
(measured at the antenna
connector)
M.Zargari et al. JSSC-08
(Measured at Soc)
P.B.Leong et al. ISIC-07
(Measured at Soc)
802.11b
802.11a/b/g/n
802.11a/b/g & BT
Receiver Specifications
Receiver Sensitivity
6Mbps/54Mbps (dBm)
-89/-73
-93 @ 2Mbps
-88 @ 11Mbps
-92/-74
-75 @54Mbps
Receiver Noise Figure (dB)
5.5
6-7
4.0
n/a
Power consumption in
54Mbps (Legacy 802.11g)
(mW)
663
(RF Rx/Synth/BB Filter= 264
MAC/PHY/PCIE/ADC =399 )
525 mW @ 11Mbps
802.11b
n/a
315
(RFRx/Synth/Filter/ADC) excluding
PMU efficiency
Power consumption in
300Mbps ( MIMO 802.11n
mode) (mW)
818
(RF Rx/Synth/BB Filter= 352
MAC/PHY/PCIE/ADC =466 )
n/a
800
n/a
n/a
11
-8 @-31dB EVM
0 @ -35dB EVM
Transmitter Specifications
Output 1dB Compression
point (dBm)
19.3
Output power to meet EVM 25dB (dBm)
15.5 @ -25dB EVM
(with digital pre-disortion)
Power consumption in
54Mbps transmit rate
(Legacy 802.11g) (mW)
878 @ 15dBm output power
(RF Tx /Synth/BB Filter= 600
MAC/PHY/PCIE/DAC = 278)
Power consumption in
150Mbps transmit rate
(802.11n mode) (mW)
1007@15dBm output power
(RF Tx/Synth/Filter = 600
MAC/PHY/PCIE/DAC = 407)
Technology
Die Area
Package
90nm CMOS with 3V I/O
33 sq. mm
10x10 QFN dual row 86pin
18
810@13dBm
Output power 802.11b
11Mbps
Other Specifications
180nm CMOS
32.2 sq. mm
144 pin BGA
251
(RFTx/Synth/Filter/DAC) excluding
PMU efficiency
630 @ -5 dBm output
power
n/a
130nm, CMOS
36 sq. mm
88pin leadless
90nm CMOS
n/a
n/a
Conclusions
• Integration, isolation, and coexistence
begins from the beginning of chip planning
• One must take into account all aspects of
the final product before work begins
• Many low level decisions can only be
answered in the context of the high level
environment
Acknowledgements
• I would like to thank the Intel Mobile Wireless
Group team for all the design and testing to
support this talk
• I want to especially thank Jonathan Jensen,
Rob Derania, Ram Sadhwani, Ryan Collins and
Lei Feng for their time, testing and input.