Design/Layout Pitfalls
Test Key
• 正常chip,與test key的
die size, PE 建議兩者
需一致.
• Case Study.
兩者大小不一,會造
成PE部門在 CP 時
alignment下半部出問
題.
Design/Layout Pitfalls
Mask Layer 定位
• 兩層光罩的零點需一
致.
• Case study.
只修改一層mask時
Design/Layout Pitfalls
Die saw - ESD
• M1 will be damaged
by ESD while die saw
process before
bonding wire process.
• Solution is put the
reverse-diode or extra
ESD cell on the gate
of M1.
Design/Layout Pitfalls
Floating Node.
• Tie the gate of dummy gate
either ground or VCC,
otherwise the gate be biased at
unknown voltage.
• Make sure Node B be well
biased at some voltage while
turning off transmission gate.
Design/Layout Pitfalls
Spike - decoder
• Be ware of using
decoder to decode two
signals which change
state simultaneously.
• Spike or Glitch will
occur at output
terminal.
Design/Layout Pitfalls
Why hysteresis?
• The real cap has a ESR, and
easier pick up the noise from
noisy signal ,then bouncing
occur at output.
• Solution, using positive
feedback or hysteresis.
Design/Layout Pitfalls
電阻的W/L.
• Due to the limitation of
schematic capture the W/L
couldn’t be automatically
generated by ECS.
• Be ware of calculating the W/L
base on your design and process
sheet resistance.
Design/Layout Pitfalls
“Mirror Effect”
• Current Mirror is widely used
in analog circuitry.
• Matching rule thumb.
1. Same area.
2. Same orientation.
3. Common centroid
4. Cross couple.
Design/Layout Pitfalls
non-uniform undercutting
• Non-uniform undercutting
effects due to different etching
rate.
Design/Layout Pitfalls
Vicinity Effect
• Vicinity effect, and solution.