The BDS Circuit Synthesis System
What it Does and Doesn’t Do
What it Is
BDS (BDD Based Logic Optimization System?)
is a multi-level circuit optimization system that
uses local BDD representations for circuit
optimization
BDS is written by Congguang Yang and Maciej
Ciesielski at the University of Massachusets
How it Works (very briefly)
Builds local BDDs to represent portions of a
boolean network (and therefore can handle
arbitrarily large circuits without memory blowup)
Looks for dominators and generalized
dominators to factor and simplify the BDD
representation
What’s a Dominator, Anyway?
A “1-dominator” is a node in a BDD that is
situated on every path from the root to the “1”
terminal. Similarly, “0-dominators” are defined. It
can be shown that the presence of one of these
leads to a certain algebraic decomposition of the
BDD.
“Generalized dominators” are nodes with similar
properties with respect to other decompositions.
What it Does
Takes input as a .blif (Berkeley Logic
Interchange Format) file
Outputs a circuit in terms of not, and, or, xnor, &
implication gates
Can output in either .blif or .dot (for GraphVis)
Beats SIS (the standard multilevel circuit
minimization tool) on a handful of benchmarks
.BLIF files
Might look something like this
.model model_name
.inputs i1 i2 i3 i4
.outputs o1
.names i1 i2 i3 i4 o1
1-1- 1
10-1 1
110- 1
.end
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What it Doesn’t Do
Guarantee optimal circuits (even in small cases)
– but it does find them for some large cases
Use an arbitrary gate library
Do any internal don’t care based optimization
Circuit Optimization
- starring don’t cares
One paradigm of circuit optimization is to iteratively look
at relatively small subcircuits, and replace them with
optimized versions.
It is almost inevitable that the subcircuits will never
recieve certain input configurations, or alternatively that
certain output configurations are completely equivalent.
This yields more freedom in the choice of a replacement
subcircuit – which of course can lead to smaller circuits.
Don’t Cares
-in two flavors
Satisfiability: The set of inputs that will never
occur to a given subcircuit.
Observability: The set of inputs for which the
subcircuit does not affect the circuit’s value
The union of these sets form the don’t care set of
a subcircuit
Don’t Cares
-in quantum circuits
Quantum computers have don’t care’s of their
own
The “work bits” ubiquitous in quantum algorithms
are the reversible equivalent of classical don’t
cares (why?)
Because of the probabilistic measurement step,
a new sort of don’t cares (with no classical
analogue) is introduced.