An Efficient SoC Test Technique by
Reusing On/Off-Chip Bus Bridge
Adviser:
Chao-Lieh Chen
Student:
Shih-Hao Lin
Yi-Ming Huang
Keng-Chih Liu
0052802
0052811
0052810
Outline








Introduction
Proposed TAM for AMBA-based SOC
Proposed Test-Access Architecture
On/Off-Chip Bus Bridge With Test Controllability
Operation of the TR-Bridge
Project
Schedule
Division of work
Introduction
Proposed TAM for AMBA-based SOC




The main contribution of our technique is to reuse the on/off
chip bus bridge as a test interface during the test mode.
The AHB master component on the bridge is reused as an
interface between the ATE and the chip under test, and then,
the ATE acts as a virtual bus master.
By utilizing the functional buses as dedicated test paths and
eliminating the bus-direction turnaround delays.
In this paper, the bridge with the test controllability is referred to
as a test-ready bridge.
Proposed Test-Access Architecture
On/Off-Chip Bus Bridge With Test
Controllability
On/Off-Chip Bus Bridge With Test
Controllability
Operation of the TR-Bridge
Project

Midterm project
AHB bus

Final project
Hybrid Test Interface Controller
Schedule
Date
Progress
Date
Progress
10/25
Propose paper
12/06 Implement final project
11/01
Implement midterm project
12/13 Implement final project
11/08
Simulation
12/20 Simulation
11/15
Implement final project
12/27 Test final project
11/22
Implement final project
01/03 Test final project
11/29
Implement final project
01/10 Demo result
Division of work

Shih-Hao Lin
撰寫程式實現HTIC區塊

Yi-Ming Huang
撰寫程式實現AHB Master區塊

Keng-Chih Liu
搜尋實現過程中之相關資訊
Q:



TIC and HTIC difference
Functional test V.S. Structural test
Test Stimuli
TIC and HTIC difference(1/2)
AMBA™ Specification (Rev 2.0)
TIC and HTIC difference(2/2)
Functional test V.S. Structural test
Test Stimuli