IMPACT OF INTER-CARRIER INTERFERENCE (ICI) ON MIMO

advertisement
Different
Microprocessors
Tamanna Haque Nipa
Lecturer
Dept. of Computer Science
Stamford University Bangladesh
Difference between 8086 &8088
External Data Path: 8 bit for 8088 and 16 bit
for 8086
 Memory Access: 8088 access memory in byte
while 8086 can access memory both bytes and
words.
 8086 has faster clock rate and better
performance then 8088.
 8088 is less expensive than 8086.

80186/80188






Enhanced version of 8086/8088
The 6/8 MHz clock provides 2 times greater
throughput than the 5MHz 8086/8088.
68 pin package
On chip priority interrupt controller chip to provide 5
interrupt pins
1 megabyte of memory can be addressed
Instructions set as 8086 and 10 new instructions
(extended instruction set)
8086/8088
General
Registers
ALU
16 bit data
or operand
request
Control
Segment
Register
Bus
Interface
Prefetcher
Prefetch
Instruction
Instruction
Decoder
Prefetch
queue
20 bit address
bus
multiplexed
with data bus
8086/8088

2 units:
 Execution
unit
 Bus interface unit

Both units are independent and operates
parallel to each other to maximized th
performance.
Execution unit





It executes all instructions as well as manipulating the
general registers and the status and control flags.
It sends data and address to the BIU when required
Instructions are fed to EU over 8 bit wide prefetch
queue bus
Instructions are processed by the control system
ALU, registers and internal data path are 16 bits wide
Bus Interface Unit



The BIU processes all requestes from the EU to read
data from or write data to memory or I/O device
All requests pass through to BIU and it combines the
segment and offsets to form the physical address
using a dedicated hardware adder
Prefetch queue is a small FIFO RAM array, used to
prefetch instruction following the current executing
instruction for EU when the BIU is free
Bus Interface Unit




Prefetch queue in 8088 hold 4 bytes and BIU begins a
fetch cycle whenever one or more bytes empty in the
queue.
Prefetch queue in 8086 hold 6 bytes and BIU begins a
fetch cycle whenever one or more bytes empty in the
queue.
When an instruction causes program control to be
transferred to the non-sequential location then the
prefetch instruction no longer be valid.
Then BIU flushes the prefetch queue and immediately
starts an instruction fetch at the target address.
Features of 80286







24-bit address bus.
16 bit data bus
Able to address 16 MB of physical memory.
It has a MMU[memory management unit]
68 pins
6 times faster than 8086
Used for multiuser and multitasking
80286

It operates in 2 modes
 Real
address mode: behaves like 8086 and
program for 8086 can run directly.
 Protected virtual address mode: it supports
maltitasking, so several program runs at the same
time and memory protection is required to protect
the memory used by one program from the action
of other program
 Can address 16 megabye of physical address in
protected mode and 1 GB of virtual memory.
Features of 80286 cont…

Register organization of 80286
 Eight
16-bit general purpose registers
 Four 16-bit segment registers
 Status & control registers
 Instruction pointer
Address unit
80286
Execution Unit
General
Registers
ALU
Physical
Address
Generator
16 bit
offsets
and data
Segment
Registers
Segment
Descriptor
Cache
Instruction
Decoder
Decoded
instruction
Bus
Interface
Address
bus 24
bits
Prefetcher
Operand
request
Control
Physical
address
(24 bits)
Decoded
Instruction
Queue
Instruction Unit
Prefetch
Queue
BIU
Data
bus 16
bits
Processing Unit

4 Processing Unit
 Address
unit
 Bus
unit
 Instruction unit
 Execution unit

All units are independent and operates
asynchronously and in parallel with the
others.
Execution unit




Execution unit manipulates the general register
as well as the status and control flags and
executes all instructions.
The ALU performs the arithmetic and logical
operations that are required by the instruction.
ALU also maintain the CPU status and control
flags.
General registers are used to moves data to or
from the registers as required.
BUS Interface Unit
It handles all communications and data
transfer between CPU and the system
bus.
 It generates the address, commands and
data signals required to access memory
and I/O devices.
 Data and address bus are not multiplexed.
 The BIU uses the idle bus cycles to prefetch instructions

BUS Interface Unit cont…
Pre-fetch queue is 6 bytes long and
whenever 2 or more bytes of pre-fetch
queue becomes empty the pre-fetch cycle
occurs.
 A control transfer instruction causes the
BIU flush the queue and immediately
begin loading the instruction from the new
address.

The Instruction Unit
It decodes the pre-fetched instruction
bytes for execution unit.
 Up to 3 fully decoded instructions are
available in the queue provided by the
instruction unit.

The Address Unit




In real mode the address unit works same as in the
8086. segment and offset values are summed together
by a dedicated adder to produce a physical memory
address.
In protected mode, every memory references, including
code pre-fetches, must be checked against the
permissions and segment limits of the current task to
detect memory protection violations.
After the permission, the logical address needs to
translate to a physical address for use by the BIU.
A cache has been designed into the address unit named
segment descriptor cache register.
The Address Unit



One segment descriptor cache register is
provided for each of the four segment register.
When a segment register is loaded with a new
value, the segment descriptor specifying access
right, segment base address and address size
associated with that value is automatically
loaded into the appropriate segment descriptor
cache register.
segment descriptor cache register is only
accessed by the address unit.
80386


Similar to 80286 but enhanced
6 parts:
 BIU
 Code Prefetch Unit
 Instruction Decode unit
 Execution Unit
 Segmentation
 Paging Unit


Unit
Six level of pipelining makes it more faster
Each part can work independently and parallel to
each other. So different part can process different
instruction at a time.
80386
Segmentation Unit
Paging Unit
Segment
register
Translation
Lookaside
buffer
Effective
address 32 bits
Segment
Descriptor
Cache
Execution Unit
Protection test
unit
General
Registers
Barrel shifter
Segment
translator
Page
translator
Address
bus
Physical
address
Linear
address
BIU
Operand
request
ALU
Multiply/Divide
Control
Decoded
instruction
Instruction Decode
Unit
Instruction
decoder
Decoded
Instruction
Queue
Prefetcher
Prefetch
Queue
Code prefetch unit
Data
bus
Additional hardware

The performance of 80386 has been also
improved by some additional hardware
 64
bit barrel shifter: a specialized hardware that
performs multiple bit shifts in a single clock cycle.
 3 input adder dedicated to effective address
processing
 An early-out multiplier : terminates the multiply
algorithm when no significant digits remain to be
processed.
386DX and 386SX
Difference between 80386DX and 80386SX is
the width of the external address and data
buses. Internally both uses 32 bit pathways.
 The address bus of 386DX is 32 bits wide and
can directly address 4 gigabytes (232 bytes) of
physical memory
 The address bus of 386SX is 24 bits wide and
can directly address 16 Mb (224 bytes) of
physical memory

Bus Interface Unit




All requests for access to the bus that comes from the
other on chip processing unit passes through the BIU
Because of the parallel operation of other parts of the
microprocessor, it is possible that more than one bus
request may be received by the BIU at the same time
BIU also queue and prioritize these requests. To avoid
the delaying program execution, request from EU
have highest priority
Every unit can independently communicate with BIU.
The Code Pre-fetch Unit
Operates same as 80286
 80386 can store 16 bytes of prefetch
instrution

The instruction decode unit
3 decoded instruction can be saved in
decoded instruction queue
 Same as 80286

Execution Unit




The function of the EU can be divided into 3 major
parts:
Control unit: the function of control unit is to speed
up certain types of operations including multiplies,
divides and effective address calculations.
Data unit: it contains ALU and eight 32 bit general
registers of the 80386. it includes 64 bit barrel shifter
and an early out multiplier.
The protection test unit: it monitors memory to detect
segmentation violations.
Segmentation unit
It performs the first stage of address
translation, converting the logical address
to linear address.
 Segment descriptor caches are employed
both to speed up the translation and to
allow protection violations to be detected
without performance.
 The dedicated 3 input adder is also used
to speed up

The paging unit
It translate the linear address to physical
address.
 If paging unit is not enable then physical
address is the same as linear address .
 It contains a cache called translation
lookaside buffer (TLB), which holds 32
most recently used page table entries.

80486 Microprocessor




The 32-bit 80486 is the next evolutionary step up from the
80386.
One of the most obvious feature included in a 80486 is a built
in math coprocessor. This coprocessor is essentially the same
as the 80387 processor used with a 80386, but being integrated
on the chip allows it to execute math instructions about three
times as fast as a 80386/387 combination.
80486 is an 8Kbyte code and data cache.
To make room for the additional signals, the 80486 is
packaged in a 168 pin, pin grid array package instead of the
132 pin PGA used for the 80386.
32 – bit Data Bus
32
32
32 – bit Data Bus
Linear Address Bus
BUS
INTERFACE
32
Barrel
Shifter
Register
File
Segmentation
Unit
Base /
Index
Bus
32
ALU
Paging Unit
2
Translation
Lookaside
Buffer
Physical
Address
8k Byte
Cache
32
Write
Buffers
Data Bus
Treansceivers
Displacement Bus
32
BRDY#
BLAST#
Control
Rom
Prefetcher
Bus Size
Control
KEN#
FLUSH#
AHOLD,
EADS#
Cache
Control
Control and
Protection
test Unit
Instruction
Decode
Decode
Instruction
Path
Code 32 Byte Code
Stream
Queue
24
D0 - D31
Bus Control
Request
Sequencer
Burst Bus
Control
Micro Instruction
F.P. Register
File
Address
Drivers
32
128
Floating
point Unit
32
A2 – A 31
BE0# - BE3#
20
Descriptor
Register
Limit and
Attribuite PLA
Cache
Unit
Parity Generation
and Control
PCHK# DP0-DP3
Pentium Processor
Download
Related flashcards
Create Flashcards