Automated Generation of
Functional Verification
for MPSoC
Marcela Šimková
Head of Verification and Testing,
Codasip Ltd.
April30,
30,2014
2014
April
1
Motivation
 MPSoC (Multi-Processor Systems on Chip):
Increase in design complexity = increase in verification complexity
 Functional verification is time-demanding:




implementation of verification environments,
preparation of different test scenarios,
preparation of reference models,
long verification runs.
 Demand for verification tools, which are:
SOFTWARE AWARE
TIME-EFFECTIVE
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AUTOMATED
2
MPSoC Design
 Processors (general purpose, ASIPs, combination) + peripherals:
 IP cores,
 in-house development.
 MPSoC description languages:
 Hardware Description Languages (HDL), like VHDL, Verilog,
 Architecture Description Languages (ADL), like CodAL, nML.
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MPSoC Verification
 Different verification approaches: functional, formal, ABV, CDV, verification
IPs, emulation, etc.
 Incremental verification:
 TREND: system-level verification (hardware + software).
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Proposed Solution
MPSoC Design
MPSoC Verification
 Support of several frontends
for HDL, ADL, etc.
 Automated generation of UVM
verification environments:
 Library of available processors.
 Intermediate representation in
IP-XACT standard:
 complex architecture description,
 interconnections,
 extendibility.
 flexible (processors with SW,
peripherals)
 complete (UVM basic components,
scoreboarding structures, coverage
monitors)
 Automated generation of reference
models.
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Extraction
 For automated generation of UVM environments, we need to extract
information about:
 interconnection of components,
 direction of interface signals (driver vs. monitor),
 stimulation of input interface signals.
 Two approaches:
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UVM Generation Challenges
 Generating reference models.
 From high-level ADL description (top-down approach).
 Instruction-set simulators for processors, simulation models for components.
 DPI connection to reference model for all components of MPSoC or a sub-set
of them.
 Setting coverage targets, assertions.
 Basic set of coverage targets and assertions is pre-generated.
 Support of functional, assertions, and code coverage.
 High-level verification management.
 1:1 or 1:N mapping of software applications to processors.
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UVM Generation
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UVM Generation
 Sobel edge detection MPSoC designed in Codasip Framework [1].
 16-bit low-power cache-less Codix-STREAM [2] processors.
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Demonstration Example - GUI
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Generated UVM Environment
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Verification OK
GM Output Picture
Input Picture
DUT Output Picture
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Inserted Bug
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Verification Failure
GM Output Picture
Input Picture
DUT Output Picture
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Configuration of Controllers
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Bug Detection in Simulator
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Conclusion
 Automated generation of MPSoC functional verification environments.
 Two approaches for extraction of information:
 analysis of ADL components,
 analysis of RTL/Netlist components.
 Generating reference models, coverage scenarios and assertions.
 High-level verification management (SW aware MPSoC verification).
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