Chapter 1
Computer System Overview
Slides from:
Operating Systems:
Internals and Design Principles
By William Stallings
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Carlos Alberto Rincon Castro | carincon@uh.edu
Operating System
• Exploits the hardware resources of one or
more processors
• Provides a set of services to system users
• Manages secondary memory and I/O devices
2
Basic Elements
Processor
I/O
Modules
Main
Memory
System
Bus
3
Processor
Controls the
operation of the
computer
Performs the data
processing
functions
Referred to as the
Central Processing
Unit (CPU)
4
Main Memory
• Stores data and programs
• Volatile
• Contents of the memory is lost when the
computer is shut down
• Referred to as real memory or primary memory
5
I/O Modules
Secondary
memory devices
(e.g. disks)
Move data between
the computer and
its external
environment
Communications
equipment
Terminals
6
System Bus
• Provides for communication among
processors, main memory, and I/O modules
7
Computer System
CPU
Main Memory
PC
MAR
IR
MBR
0
1
2
System
Bus
Instruction
Instruction
Instruction
I/O AR
Execution
unit
Data
Data
Data
Data
I/O BR
I/O Module
Buffers
n-2
n-1
PC
=
IR
=
MAR =
MBR =
I/O AR =
I/O BR =
Program counter
Instruction register
Memory address register
Memory buffer register
Input/output address register
Input/output buffer register
Figure 1.1 Computer Components: Top-Level View
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
8
Microprocessor
• Invention that brought about desktop and
handheld computing
• Contains a processor on a single chip
• Fastest general-purpose processors
• Multiprocessors
• Each chip (socket) contains multiple
processors (cores)
9
Graphical Processing Units (GPU’s)
• Provide efficient computation on arrays of data
using Single-Instruction Multiple Data (SIMD)
techniques pioneered in supercomputers
• No longer used just for rendering advanced
graphics
• Also used for general numerical processing
• Physics simulations for games
• Computations on large spreadsheets
• AI
10
Digital Signal Processors (DSPs)
• Deal with streaming signals such as audio or
video
• Used to be embedded in I/O devices like
modems
• Are now becoming first-class computational
devices, especially in handhelds
• Encoding/decoding speech and video
(codecs)
• Provide support for encryption and security
11
System on a Chip (SoC)
• To satisfy the requirements of handheld
devices, the classic microprocessor is giving
way to the SoC
• Other components of the system, such as
DSPs, GPUs, I/O devices (such as
codecs and radios) and main memory, in
addition to the CPUs and caches, are on
the same chip
12
Instruction Execution
• A program consists of a set of instructions
stored in memory
Processor reads
(fetches) instructions
from memory
Processor executes
each instruction
Two steps
13
Instruction Cycle
START
Fetch Stage
Execute Stage
Fetch Next
Instruction
Execute
Instruction
HALT
Figure 1.2 Basic Instruction Cycle
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
14
Instruction Fetch and Execute
• The processor fetches an instruction from
memory
• The program counter (PC) holds the address
of the next instruction to be fetched
 PC is incremented after each fetch
15
Instruction Register (IR)
Fetched instruction is
loaded into Instruction
Register (IR)
• Processor interprets the
instruction and performs
required action:
• Processor-memory
• Processor-I/O
• Data processing
• Control
16
Hypothetical Computer System
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
17
Hypothetical Computer System
# Type of Instructions = 2 ^ (size opcode in bits)
# Type of Instructions = 2 ^ 4 = 16
Mem size (bytes) = # positions * position size in bytes
# positions = 2 ^ (address size in bits)
# positions = 2 ^ 12 = 4096
Mem size = 4096 * 2 bytes = 8192 bytes
Memory Range: 000 – FFF
Data Range: 0000 – FFFF
18
Hypothetical Computer System
Fetch Stage
Memory
300 1 9 4 0
301 5 9 4 1
302 2 9 4 1
Execute Stage
CPU Registers
Memory
300 1 9 4 0
3 0 0 PC
AC 301 5 9 4 1
1 9 4 0 IR 302 2 9 4 1
•
•
•
•
940 0 0 0 3
941 0 0 0 2
940 0 0 0 3
941 0 0 0 2
Step 1
Step 2
Memory
300 1 9 4 0
301 5 9 4 1
302 2 9 4 1
CPU Registers
Memory
300 1 9 4 0
3 0 1 PC
0 0 0 3 AC 301 5 9 4 1
5 9 4 1 IR 302 2 9 4 1
•
•
CPU Registers
3 0 2 PC
0 0 0 5 AC
5 9 4 1 IR
•
•
940 0 0 0 3
941 0 0 0 2
940 0 0 0 3
941 0 0 0 2
Step 3
Step 4
Memory
300 1 9 4 0
301 5 9 4 1
302 2 9 4 1
CPU Registers
3 0 1 PC
0 0 0 3 AC
1 9 4 0 IR
CPU Registers
Memory
PC
300
3 0 2
1 9 4 0
0 0 0 5 AC 301 5 9 4 1
2 9 4 1 IR 302 2 9 4 1
•
•
3+2=5
CPU Registers
3 0 3 PC
0 0 0 5 AC
2 9 4 1 IR
•
•
940 0 0 0 3
941 0 0 0 2
940 0 0 0 3
941 0 0 0 5
Step 5
Step 6
Figure 1.4 Example of Program Execution
(contents of memory and registers in hexadecimal)
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
19
Interrupts
• Mechanism by which other modules may
interrupt the normal sequencing of the
processor
• Provided to improve processor utilization
• Most I/O devices are slower than the
processor
• Processor must pause to wait for device
• Wasteful use of the processor
20
Interrupts
Classes of Interrupts
Program
Generated by some condition that occurs as a result of an
instruction execution, such as arithmetic overflow, division
by zero, attempt to execute an illegal machine instruction,
and reference outside a user's allowed memory space.
Timer
Generated by a timer within the processor. This allows the
operating system to perform certain functions on a regular
basis.
I/O
Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety of error
conditions.
Hardware
failure
Generated by a failure, such as power failure or memory
parity error.
21
Flow of Control
UserUser
Program
Program
1
User
I/O I/O
UserUser
Program
Program
Program Program
Program
4
1
WRITE
WRITE
4
I/O I/O
Command
Command
5
1
1 1
WRITE
WRITE
WRITE
User
I/O I/OI/O
UserUser
Program
Program
Program
ProgramProgram
Program
I/O I/OI/O
Program
Program
Program
4 4 1
4
4
1 1
I/O I/OI/O
Command
Command
Command
WRITE
WRITE
WRITE
5
2a 2a
2a
2
2
2
Interrupt
Interrupt
Handler
Handler
2b 2b
WRITE
WRITE
WRITE
5
5
2
2b
Interrupt
Interrupt
Interrupt
Handler
Handler
Handler
WRITE
WRITE
WRITE
5
ENDEND
3
3b 3b
WRITE
WRITE
WRITE
(a) interrupts
No interrupts
(a) No
WR
3a
3
WRITE
WRITE
5 5
END
ENDEND
3a 3a
3
WR
END
2
WRITE
WRITE
I/O I/OI/O
Command
Command
Command
1
5
ENDEND
2
4 4
Us
Prog
(b) Interrupts;
I/O wait
(a)short
Noshort
interrupts
(b) Interrupts;
I/O wait
3
3
3
3b
WRITE
WRITE
WRITE
WR
Interrupts;
short
(c)(b)
Interrupts;
I/OI/O
waitwait
(c) Interrupts;
longlong
I/O
wait
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
= interrupt
occurs
during
course
of execution
of user
=program
interrupt
program
occurs during course of execution of user program
= interrupt
occurs
during
course
of execution
of user
22
Interrupts
Time
1
1
4
4
I/O operation;
processor waits
5
2a
I/O operation
concurrent with
processor executing
5
2b
2
4
4
3a
I/O operation;
processor waits
5
3
I/O operation
concurrent with
processor executing
5
3b
(b) With interrupts
(a) Without interrupts
Figure 1.8 Program Timing: Short I /O Wait
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
23
Interrupts
Time
1
1
4
4
I/O operation;
processor waits
2
5
I/O operation
concurrent with
processor executing;
then processor
waits
5
2
4
4
3
I/O operation;
processor waits
I/O operation
concurrent with
processor executing;
then processor
waits
5
5
3
(b) With interrupts
(a) Without interrupts
Figure 1.9 Program Timing: Long I /O Wait
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
24
Interrupts
User Program
I nterrupt Handler
1
2
Interrupt
occurs here
i
i+1
M
Figure 1.6 Transfer of Control via I nterrupts
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
25
Interrupts
Fetch Stage
Execute Stage
I nterrupt Stage
I nterrupts
Disabled
START
Fetch next
instruction
Execute
instruction
Check for
interrupt;
initiate interrupt
I nterrupts
handler
Enabled
HALT
Figure 1.7 I nstruction Cycle with I nterrupts
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
26
Interrupts
Hardware
Device controller or
other system hardware
issues an interrupt
Processor finishes
execution of current
instruction
Software
Save remainder of
process state
information
Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt
Figure 1.10 Simple I nterrupt Processing
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
27
Interrupts
T– M
T– M
Y
Control
Stack
T
Y
Control
Stack
N+1
T
Start
Interrupt
Service
Y + L Return Routine
N+1
Y+ L + 1
Program
Counter
Program
Counter
General
Registers
Start
Y
Interrupt
Service
Y + L Return Routine
Stack
Pointer
T– M
Stack
Pointer
Processor
Processor
T
T– M
N
N+ 1
General
Registers
User's
Program
M ain
M emory
(a) I nterrupt occurs after instruction
at location N
T
N
N+1
User's
Program
M ain
M emory
(b) Return from interrupt
Figure 1.11 Changes in M emory and Registers for an I nterrupt
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
28
Multiple Interrupts
An interrupt occurs
while another interrupt
is being processed
Two approaches:
• e.g. receiving data from a
communications line and
printing results at the
same time
• Disable interrupts while an
interrupt is being
processed
• Use a priority scheme
29
Multiple Interrupts
User Program
I nterrupt
Handler X
I nterrupt
Handler Y
(a) Sequential interrupt processing
User Program
I nterrupt
Handler X
I nterrupt
Handler Y
(b) Nested interrupt processing
Figure 1.12 Transfer of Control with M ultiple I nterrupts
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
30
Multiple Interrupts
Printer
interrupt service routine
User Program
Communication
interrupt service routine
t=0
t
0
=1
t=
15
t = 25
t=
40
t = 25
t=
Disk
interrupt service routine
35
Figure 1.13 Example Time Sequence of M ultiple I nterrupts
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
31
Memory Hierarchy
• Design constraints on a computer’s memory
How much?
How fast?
How expensive?
• If the capacity is there, applications will likely be
developed to use it
• Memory must be able to keep up with the processor
• Cost of memory must be reasonable in relationship to
the other components
32
Memory Relationships
Faster access
time =
greater cost
per bit
Greater capacity =
smaller cost per bit
Greater capacity
= slower access
speed
33
The Memory Hierarchy
 Going down the hierarchy:
I nb
M e oar d
mo
ry
Decreasing cost per bit
Increasing capacity
Increasing access time
Decreasing frequency of
access to the memory by
the processor
Ou
t
Sto boar
r ag d
e
Of
Sto f-line
r ag
e
gRe r s
e
ist
e
ch
Ca
in
M a or y
m
e
M
sk
Di
tic
ne OM
g
M a D- R W
C D -R W
R M
C
DD V D- R A y
a
DV lu-R
B
M
tic
ne
ag
pe
Ta
Figure 1.14 The M emory Hierarchy
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
34
Two-level Memory System
T1 + T2
Average access time
T2
T1
0
1
Fraction of accesses involving only Level 1 (Hit ratio)
Figure 1.15 Performance of a Simple Two-Level M emory
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
35
Two-level Memory System
Access time Level 1 (TL1) = 100 ms
Access time Level 2 (TL2) = 1000 ms
Hit Ratio = 90 %
Miss Ratio = 10%
Average Access time (AvgT) = HR * TL1 + MR * (TL2+TL1)
AvgT = 0.9 * 100 ms + 0.1 * (1000 ms + 100 ms)
36
Principle of Locality
• Memory references by the processor tend to
cluster
• Data is organized so that the percentage of
accesses to each successively lower level is
substantially less than that of the level above
• Can be applied across more than two levels of
memory
37
Secondary Memory
Secondary
Memory
Also
referred to
as auxiliary
memory
• External
• Nonvolatile
• Used to store
program and
data files
38
Cache Memory
• Invisible to the OS
• Interacts with other memory management hardware
• Processor must access memory at least once per
instruction cycle
• Processor execution is limited by memory cycle time
• Exploit the principle of locality with a small, fast
memory
39
Cache Memory
Block Transfer
Word Transfer
M ain M emory
Cache
CPU
Fast
Slow
(a) Single cache
Level 2
(L2) cache
Level 1
(L1) cache
CPU
Fastest
Fast
Level 3
(L3) cache
Less
fast
M ain
M emory
Slow
(b) Three-level cache organization
Figure 1.16 Cache and M ain M emory
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
40
Cache Memory
Line
Number Tag
0
1
2
Block
Memory
address
0
1
2
3
Block 0
(K words)
C-1
Block Length
(K Words)
(a) Cache
Block M – 1
2n - 1
Word
Length
(b) Main memory
Figure 1.17 Cache/M ain-M emory Structure
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
41
Cache Memory
START
RA - read address
Receive address
RA from CPU
Is block
containing RA
in cache?
Access main
memory for block
containing RA
No
Yes
Allocate cache
slot for main
memory block
Fetch RA word
and deliver
to CPU
Load main
memory block
into cache slot
Deliver RA word
to CPU
DONE
Figure 1.18 Cache Read Operation
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
42
Cache Memory Design Aspects
Cache
size
Number
of cache
levels
Block size
Main
categories
are:
Write
policy
Mapping
function
Replacement
algorithm
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
43
Cache and Block Size
Cache Size
Small caches have
significant impact
on performance
Block Size
The unit of data
exchanged
between cache
and main memory
44
Mapping Function
 Determines which cache location the block will
occupy
When one block is read in,
another may have to be
replaced
Two constraints affect
design:
The more flexible the
mapping function, the more
complex is the circuitry
required to search the cache
45
Cache Replacement Algorithm
 Chooses which block to replace when a new block is
to be loaded into the cache.
 Least Recently Used (LRU) Algorithm
 Effective strategy is to replace a block that has been
in the cache the longest with no references to it
 Hardware mechanisms are needed to identify the
least recently used block
46
Write Policy
Dictates when the memory write operation
takes place
• Can occur every time the block is updated
• Can occur when the block is replaced
• Minimizes write operations
• Leaves main memory in an obsolete state
47
I/O Techniques
When the processor encounters an instruction relating to I/O,
it executes that instruction by issuing a command to the
appropriate I/O module
Three techniques are possible for I/O
operations:
Programmed
I/O
InterruptDriven I/O
Direct Memory
Access (DMA)
48
Programmed I/O
• The I/O module performs the requested action then
sets the appropriate bits in the I/O status register
• The processor periodically checks the status of the
I/O module until it determines the instruction is
complete
• With programmed I/O the performance level of the
entire system is severely degraded
49
Interrupt-Driven I/O
Processor
issues an I/O
command to
a module
and then
goes on to do
some other
useful work
The processor
executes the
data transfer
and then
resumes its
former
processing
The I/O module will
then interrupt the
processor to request
service when it is
ready to exchange
data with the
processor
More efficient than
Programmed I/O but
still requires active
intervention of the
processor to transfer
data between
memory and an I/O
module
50
Interrupt-Driven I/O Drawbacks
• Transfer rate is limited by the speed with which
the processor can test and service a device
• The processor is tied up in managing an I/O
transfer
 A number of instructions must be
executed for each I/O transfer
51
Direct Memory Access (DMA)
When the processor wishes to read or write
data it issues a command to the DMA module
containing:
• Whether a read or write is requested
• The address of the I/O device involved
• The starting location in memory to read/write
• The number of words to be read/written
Performed by a separate module on the system bus or
incorporated into an I/O module
52
Direct Memory Access (DMA)
• Transfers the entire block of data directly to
and from memory without going through the
processor
• Processor is involved only at the beginning and end of
the transfer
• Processor executes more slowly during a transfer when
processor access to the bus is required
• More efficient than interrupt-driven or
programmed I/O
53
Symmetric Multiprocessors (SMP)
• A stand-alone computer system with the following
characteristics:
• Two or more similar processors of comparable capability
• Processors share the same main memory and are
interconnected by a bus or other internal connection
scheme
• Processors share access to I/O devices
• All processors can perform the same functions
• The system is controlled by an integrated operating system
that provides interaction between processors and their
programs at the job, task, file, and data element levels
54
SMP Advantages
Performance
Scaling
• A system with multiple
processors will yield greater
performance if work can be
done in parallel
• Vendors can offer a range of
products with different price
and performance
characteristics
Availability
Incremental Growth
• The failure of a single
processor does not halt the
machine
• An additional processor can
be added to enhance
performance
55
Symmetric Multiprocessors (SMP)
Processor
Processor
Processor
L1 Cache
L1 Cache
L1 Cache
L2 Cache
L2 Cache
L2 Cache
System Bus
M ain
M emory
I /O
Subsystem
I /O
Adapter
I /O
Adapter
I /O
Adapter
Figure 1.19 Symmetric M ultipr ocessor Organization
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
56
Multicore Computer
• Also known as a chip multiprocessor
• Combines two or more processors (cores) on a
single piece of silicon (die)
• Each core consists of all of the
components of an independent processor
• In addition, multicore chips also include L2
cache and in some cases L3 cache
57
Multicore Computer
© Pearson Education, Inc., Hoboken, NJ. All rights reserved.
58
Summary
• Basic Elements
• Evolution of the
microprocessor
• Instruction execution
• Interrupts
• Interrupts and the
instruction cycle
• Interrupt
processing
• Multiple interrupts
• The memory hierarchy
• Cache memory
• Motivation
• Cache principles
• Cache design
• Direct memory access
• Multiprocessor and Multicore
organization
• Symmetric
multiprocessors
• Multicore computers
59