SCHOOL OF ELECTRONICS ENGINEERING
NANOTECHNOLOGY DEPARTMENT
DIGITAL ASSIGNMENT
Fall Semester 2025-26
COURSE CODE: MAVLD504
COURSE NAME: ANALOG IC DESIGN – ELA
FACULTY NAME: KUMARAVEL S
REG NO: 25MVD0025
NAME: ARAVIND KRISHNA D R
Simulation of I/V, Gm/Id plots for NMOS and PMOS device
Aim:
To simulate the I/V and Gm/Id plots for NMOS and PMOS device.
Apparatus required:
Cadence Virtuoso – umc 180nm technology
Circuit:
NMOS:
PMOS:
Plots:
NMOS:
Id vs Vds with varying Vgs:
Id vs Vgs with varying Vbs:
Ft vs Gm/Id:
Red – Ft
Yellow – Id/W
Id/W vs Gm/Id for varying Length:
PMOS:
Id vs Vsg for varying Vbd:
Id vs Vsd for varying Vsg:
Ft vs Gm/Id:
Yellow – Ft
Red – Id/W
Id/W vs Gm/Id:
Procedure:
1. Create the circuit as given in the above image for NMOS.
2. Change the Width as 1 um and Length as 500 nm.
3. Open ADE, select copy from cell from variables and give Vds=0.5, Vgs=0 and Vbs=0
for the Id vs Vgs graph.
4. In Analysis, select dc and the select “Save DC operating point”, after this sweep Vgs
from 0 to 1.8 V.
5. Go to outputs, then select “to be plotted – Select on design” and then select the drain
of NMOS.
6. Go to results and after selecting the parametric analysis select Vbs and sweep from 1.8 to 0 V.
7. Now run to get the graph of Id vs Vgs to find out the threshold voltage for different
Vbs.
8. Similarly give Vgs=0, Vds=0 and Vbs=0 in the variables section for the Id vs Vds
graph.
9. In the parametric analysis select Vgs and weep from 0 – 1.8 V
10. Now run again to get the graph of Id vs Vds for different Vgs.
11. Similarly, for PMOS, invert the voltage sources at the gate and drain. Let the body
voltage Vbd be connected same like NMOS.
12. Now at the output select source of the PMOS.
13. Now run to get the graph of Is vs Vsg to find out the threshold voltage for different
Vbs and the graph of Is vs Vsd for different Vsg.
14. We do this to get the output at the first quadrant as the electrons move from drain to
source in PMOS.
15. After getting these plots go to the command window and type “gedit saveop.scs” and
then click enter.
16. In the savop file type “save M0:all”, where M0 is the instance name (MOSFET’s
name in the circuit)
17. In ADE go to setup – Simulation Files and then add this “saveop” file under the
“stimulus files” then click ok.
18. Now, choose results browser under tools.
19. Expand the path and select and plot the following that are located in DC:
M0/D, Cgg, gm, gmoverid – For NMOS
M0/S, Cgg, gm, gmoverid – For PMOS
Now, under instances, select the transistor’s instance name and select ‘w’ for both
NMOS and PMOS.
20. Send all these plots to the calculator and compute Ft = gm/(2*3.14*Cgg), Id/w.
21. Now send these values to ADE and rename them as Ft and Id/w.
22. Now plot gmoverid, Ft, Id/w vs Vgs.
23. Now change the x axis to gmoverid.
24. Now, change Length as ‘L’ in parametric analysis and sweep it from 180n to 500n to
get the Id/w vs Gm/Id for different values of Length.
25. Similarly, do it for PMOS using M0/S and its w value, but use a different stimulus
files naming it as saveop1, and give the instance name of PMOS.
Calculation:
From the graph, we could find that Vtn = 0.47 V and Vtp = -0.55V
Lambda value:
Inference:
Id vs Vgs graph for increasing Vbs:
In this graph, Id increases as Vgs increases only after a certain Vgs. It shows that the
device turns on only after a certain voltage called the ‘Threshold Voltage’. But this threshold
voltage increases as the Vsb increases, this is called ‘Body Effect’. This increase in threshold
voltage is due to the increase in gate voltage required to form the ‘Inversion Region’, which
is due to the increase in reverse bias at the p type substrate in NMOS. This is the same for
PMOS to, but the polarity and direction of current is just the opposite of NMOS.
Id vs Vds graph for increasing Vgs:
In this graph, Id increases linearly as Vds increases and then reaches a constant range,
which is called the saturation current in the saturation region. This is due to the increase in
depletion layer between the drain and body which is the effect of increase in reverse bias at
the drain and body. This pinches off the channel near the drain and therefore the constant
current is the drift current due to the high electric field. This current increases as Vgs
increases due to the increase in channel width, contributing more electrons to the current
flow. And again, this is similar in PMOS, but the polarities and the direction of current are
opposite to NMOS.
Ft vs Gm/Id:
In this graph, Ft increases sharply to a certain point and then starts to decrease
because Ft increases with a decrease in Cgg and vice versa. For a small value of Gm/Id, it is
in the strong inversion region i.e the gate capacitance is saturated and also decreases to a
certain amount due to pinch off. Here, Gm is high compared to Cgg, contributing to an
increase in Ft. As the Gm/Id (efficiency) increases, the device moves towards the weak
inversion region, where the subthreshold current due to minority carriers increase
exponentially and therefore increasing the Cgg (diffusion capacitance). This results in the
decrease in Ft as the Gm reaches a saturation level. This goes same for the PMOS but due to
less mobility, the Ft value is comparatively less.
Id/W vs Gm/Id:
In this graph, as the Gm/Id (efficiency) increases, the Id/W (drain current per width)
decreases. This states that for higher efficiency the drain current per unit width is lower in the
weak inversion region. Also as seen in the parametric analysis if the Length of the device is
increased, it even more reduces the drain current per unit width, which is very obvious as
current decreases with increase in channel length. This is exactly same for PMOS too.
Conclusion:
In this experiment, we analyzed the output characteristics of NMOS and PMOS transistors to
extract the threshold voltage (Vth) and the channel length modulation parameter (λ). For
NMOS, Vth = 0.47 V and λ = 0.109 V⁻¹; for PMOS, Vth = –0.55 V and λ = 0.154 V⁻¹. The
PMOS drain current was observed to be significantly lower than NMOS, mainly due to the
lower hole mobility.
Additionally, the FT vs Gm/ID curve showed a peak at moderate inversion levels, indicating
the optimal trade-off between speed and power. The ID/W vs Gm/ID curves helped us
understand current efficiency per unit width, which is critical for sizing devices in analog and
RF design. These curves are essential for determining the region of operation (weak,
moderate, or strong inversion) suited for performance-efficient design.