Output Load Characterization Capacitance
impact
Presented By
Boya Ramaleela
Output Load Characterization
• Output Load Characterization
is the process of analyzing how a logic
cell's output behaves when it drives
different load capacitances.
a gate does not drive only one wire. It
drives:
• Interconnect wires
• Input pins of other cells
• Parasitic capacitances
These collectively form the output load
capacitance (CL).
Capacitance Impacts: 1. CMOS inverter: First, I have drawn a CMOS inverter
•
PMOS is connected to VDD
• NMOS is connected to VSS
• Input = A
• Output = Y
• At the output node, a capacitor CL
(load capacitor) is connected.
What does CL represent ?
2. Driver Cell and Load cell: • The inverter is acting as a deriver cell.
• The gate connected after it are called
load cells.
• One inverter drivers' multiple inverters.
One output is connected to four input pins.
CL=Cpin1+Cpin2+Cpin3+Cpin4 + Cwire +
Driver o/p pin cap
• The driver must charge and discharge all
these capacitors.
3. Delay relationship: • if load capacitance increases, then
Propagation delay increases.
4. Transition Time: • When load capacitance increases
1. Rise time
increases.
2. Fall time
increases
3. Output transition
becomes a slower.