Title: Vapor Phase Covalent Organic Frameworks for Thermally Conductive Low-k Dielectrics
Submitted to: *********************************************
Date: September 2, 2025 Abram Inman
PROJECT DESCRIPTION
History: Modern electronic devices rely on integrated circuits (ICs), which use crystalline silicon
chip structures comprised of billions of transistors to process inputs and outputs. As technology
advances, these chips continue to shrink, along with the size of the transistors (switches)
conductors and insulating pathways (wires and dielectrics) creating increasingly dense networks.
While miniaturization improves performance, it also introduces challenges in managing both heat
dissipation and capacitive coupling (when the electric field from a switching signal line induces
unwanted noise on a neighboring signal line). To reduce power consumption and improve thermal
performance, materials with lower dielectric constants (k) are required SiO₂ is widely used as a
dielectric in many ICs, with a dielectric constant of 3.9 and a thermal conductivity of about 1.3
W/m·K for fused silica.3. In an article by Austin M. Evans et al.,1 COFs were shown to exhibit
ultra-low dielectric permittivity (k=1.6, meaning good electrical insulators) while also
maintaining relatively high thermal conductivity (TC~1 W/m·K), making them strong candidates
for advanced dielectric layers.
In ICs, oxide layers not only serve as electrical insulators but also play a role in thermal transport.
Unfortunately, conventional oxides have limited thermal conductivity, which restricts efficient
cooling of the silicon core. This project seeks to address that limitation by investigating covalent
organic frameworks (COFs) as a next-generation alternative to traditional oxide layers. In a study
by Liu, M. et al., 2 two-dimensional (2D) COF films were successfully synthesized in a tube oven
with a thickness of approximately 30 nm. Although the paper did not specify dielectric properties,
it provides a valuable baseline for developing general experimental procedures involving COFs.
Achieving low k dielectrics will be especially important as the industry moves into threedimensional integrated circuit design, where both electrical isolation and effective heat
management are critical.
Image 1: Dielectric layers are present in both NMOS and
PMOS transistors and are commonly used in integrated
circuits (ICs).
Objective: The objective of this experiment is to establish a
reliable procedure for the growth of covalent organic
frameworks (COFs) using vapor phase deposition techniques,
with an emphasis on chemical vapor deposition (CVD)
methods. The focus is on synthesizing COF films through
controlled vapor phase processes to achieve uniform and
high-quality layers suitable for dielectric applications.
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Following synthesis, the experiment will assess the stability of the deposited COF films by
evaluating their resistance to delamination, electrical capacitance, physical thickness, and
thermal conductance. These metrics are critical to determining the suitability of COFs as
dielectric materials.
Given the inherently porous structure of COFs, it is anticipated that these materials will
demonstrate reduced electrical conductivity, thus functioning effectively as low-k dielectrics. At
the same time, the porous architecture is expected to enhance thermal conductivity, which could
provide improved heat management capabilities compared to conventional materials.
Image 2: Tube oven layout with substrate and precursor (COF) placement
METHODS
The method used will take the substrate (Si) and place it in the chamber at the location based on
the deposition’s temperature needs. A precursor will be placed in the tube oven between the
substrate and the gas inlet (H2 and Argon). After the substrate and the precursor have been placed,
the chamber will be vacuumed down to the desired pressure setpoint, gas flows set through the
MFC’s, temperature set to the desired setpoint, and the pressure valve set to maintain the vacuum
pressure regulated. The proposed procedure: after sample and substrate placement, connect the gas
flow of argon and hydrogen.
Design Of Experiments (DOE): Place a copper sheet into the tube oven to see where the deposition
visually takes place, run this trial with three different plates, at 3 different temperatures. Record
locations and deposit substrates in those locations. Place the precursor and perform 5 trial runs for
a batch of 5 substrates for each run. The variables will be temperature, gas, and pressure. Then we
will use a mercury probe (an instrument used in the semiconductor industry to make fast, nondestructive electrical measurements on materials by using liquid mercury to form contacts) to
analyze the dielectric constant to see which ones have the desired features. The probe measures
effectively in the 10e-107 Hz range. This is important because it tells us which physical processes
we are measuring in the film, and whether your dielectric constant reflects the “intrinsic” material
or extra effects like traps, leakage, or interfacial polarization.
TIME SCHEDULE

Phase 1: Months 1–2: Optimize furnace operation and ensure reliable process control.
(Copper strips)
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
Phase 2: Months 3–5: Conduct initial deposition trials; refine process parameters.
(Trial samples)

Phase 3: Months 6-7: Systematic testing of COFs, characterization of thin films. (Produce
samples for study)

Phase 4: Month 8: Data analysis, evaluation of deposition outcome. Poster development
and printing.
STUDENT BACKGROUND
I am a senior in electrical and computer engineering at UMKC, engaged with the Missouri
Institute for Defense & Energy and MIDE since early 2024. I expect to earn my bachelor’s
degree in spring 2026 and plan to pursue a master’s in the same field. My coursework covers
logic design, electronic circuits, semiconductors, and device analysis—including MOSFETs,
FETs, BJTs, and PN/NP transistors—which directly relates to my current research. As of spring
2025, my GPA is 3.47. I have practical experience with Physical Vapor Deposition (PVD) and
substrate preparation, and am currently learning Chemical Vapor Deposition (CVD) techniques
that will support upcoming experiments.
IMPORTANCE TO STUDY
Although solvothermal synthesis of COFs is well-documented, vapor phase deposition for
semiconductor uses is not. I aim to address this by conducting deposition studies with a quartz
crystal vacuum tube furnace under Prof. Paquette's guidance. While Prof. Paquette will advise on
materials and analysis, I will focus on substrate prep, deposition, and process optimization. A
critical step is testing the best equipment setup to enhance my knowledge of modern deposition
and fabrication techniques.
BUDGET
$236.34 PID heater control, $285 replacement Quartz tube 30”, $100 Silicon wafer, $ $149/g
from TCI Chemicals Benzene-1,3,5-tricarboxaldehyde-1,3,5-triformylbenzene, $345 Methane
gas, $145 Argon gas, $96.77 PPE (Gloves and Eyewear), $129 Poster.
PWORK CITED
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1. Evans, Austin M. “Thermally Conductive Ultra-Low-k Dielectric Layers Based on TwoDimensional Covalent Organic Frameworks.” Nature Materials, U.S. National Library of
Medicine, 20 Aug. 2021, pubmed.ncbi.nlm.nih.gov/33737728/.
2. Liu, Minghui, and Youxing Liu. “Two-Dimensional Covalent Organic Framework Films
Prepared on Various Substrates through Vapor Induced Conversion.” Nature News, Nature
Publishing Group, 17 Mar. 2022, www.nature.com/articles/s41467-022-29050-9.
3. Robertson, J. “High Dielectric Constant Oxides.” ChromeExtension://Efaidnbmnnnibpcajpcglclefindmkaj/Https://Web.Stanford.Edu/Class/Ee311/N
OTES/Robertson%20JAP04.Pdf, Engineering Department, Cambridge University,
Cambridge, 2 Dec. 2004.
I will have time to make edits tomorrow. Please disregard content beyond page 3 unless the
works cited section is required, as it is assumed not to contribute to the total page count.
STUDENT BACKGROUND
I am currently a senior studying electrical and computer engineering at the University of
Missouri–Kansas City (UMKC), where I have been engaged with the Missouri Institute for
Defense & Energy and the Division of Energy (MIDE) since early 2024. My expected graduation
with a bachelor’s degree is in spring 2026, after which I intend to pursue a master’s degree in the
same field. Throughout my academic career, I have completed coursework that includes logic
design, electronic circuits, and studies of semiconductors and devices. These courses have
provided me with a solid foundation in topics such as MOSFETs, FETs, BJTs, and PN/NP
transistor characteristics, along with their analysis. The research I am undertaking is closely
related to these subjects, and I believe it will allow me to gain a deeper understanding of
technology. As of the end of spring 2025, my GPA stands at 3.47.
My classes have offered a broad overview of the relevant topics, and I am eager to further
explore the operational principles of transistors in modern devices. In addition to my academic
background, I have hands-on experience with Physical Vapor Deposition (PVD), as well as
expertise in substrate handling and preparation. I am currently expanding my knowledge by
studying the techniques and general operation of Chemical Vapor Deposition (CVD) using a tube
oven, which will be employed in the upcoming experiment.
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IGNORE THIS UNLESS YOU SEE SOMETHING I SHOULD ADD. DO I NEED TO ADD THE
CITATIONS? If so I will need to format them
This research investigates the feasibility of chemical vapor deposition (CVD) of COFs onto
silicon substrates to form functional monolayers or thin films. While solvothermal synthesis of
COFs is widely reported in the literature, their vapor phase deposition for semiconductor
applications remains underexplored.
Under the supervision of Professor Michelle Paquette (Missouri Institute for Defense &
Energy and Division of Energy, Matter & Systems, School of Science & Engineering), I will
conduct deposition studies using a quartz crystal vacuum tube furnace equipped with mass flow
controllers (MFCs). My expertise lies in electrical and computer engineering rather than chemistry,
so material selection and characterization will be guided by Prof. Paquette, while I will focus on
substrate preparation, deposition operation, and process optimization.
SIGNIFICANCE AND INNOVATION
Targeted Need: Current oxide layers in ICs exhibit suboptimal thermal conductivity, limiting
cooling efficiency as device dimensions shrink. Improved low-k dielectric materials are urgently
needed to sustain continued miniaturization and performance scaling.
Innovation: This project introduces vapor phase COF deposition to semiconductor processing, a
novel approach that combines the structural benefits of porous frameworks with the precision of
CVD techniques. Successful outcomes could establish a new class of dielectric materials that
simultaneously provide electrical insulation and enhanced thermal transport.
BACKGROUND AND APPROACH
I bring prior experience in CVD and substrate preparation, including deposition of chromium (Cr)
and copper (Cu) layers onto silicon wafers. Although COF deposition is relatively new to me, I
have been trained in tube furnace operation and will adapt that expertise to vapor phase deposition
of organic frameworks.
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The project will compare COF deposition against conventional dielectric processes to identify
deficiencies, advantages, and process feasibility. Specifically, vapor phase deposition (VPD) will
be employed to test whether stable, uniform COF films can be achieved under controlled furnace
conditions.
TASKS AND ANTICIPATED RESULTS

Develop reliable vapor phase deposition protocols for COFs.

Achieve uniform, thin COF films on silicon substrates.

Evaluate adhesion, stability, and thermal/electrical properties of deposited films.

Demonstrate potential of COFs as low-k dielectrics with improved thermal conductivity.
STUDENT BACKGROUND
I am a senior pursuing a Master of Science in Electrical and Computer Engineering with a
minor in Mathematics. I have been working at the Missouri Institute for Defense & Energy for the
past 18 months, gaining practical experience in substrate preparation, CVD processes, and vacuum
system operation. This project leverages my technical training while expanding into a novel
application under expert mentorship.
REFERENCES
1. Lab and Furnace – Chemical Vapor Deposition Explained
2. ScienceDirect – Review Article on CVD
3. Liu, M., Liu, Y., Dong, J. et al. Two-dimensional covalent organic framework films
prepared on various substrates through vapor induced conversion. Nat
Commun 13,
1411
(2022).
https://doi.org/10.1038/s41467-022-29050-9
Published17 March 2022
4. chromeextension://efaidnbmnnnibpcajpcglclefindmkaj/https://web.stanford.edu/class/ee311/NO
TES/Robertson%20JAP04.pdf
5. https://pubmed.ncbi.nlm.nih.gov/33737728/
6. Pic:
https://www.google.com/search?q=CVD%20tube%20oven%20COFs.%20examples&ud
m=2&tbs=rimg:CRVSVkxXYq9EYY-npG75F8msgIAwAIA2AIA4AIA&cs=1&hl=en&sa=X&ved=0CBoQuIIBahcKEwiwiabOt2PAxUAAAAAHQAAAAAQBw&biw=1600&bih=731&dpr=1#vhid=9ZUdrUbsxfpqL
M&vssid=mosaic
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7. https://www.nature.com/articles/s41467-022-29050-9#citeas
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