SESSION XVI: New Device and Circuit Techniques
FAM 16.5:
Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits
R. M. Swanson and J. D. Meindl
Stanford University
Stanford, Cal.
COMPLEMENTARY MOS integrated circuits are attractive for
micropower digital systems since their standby or static power
drain is lowerthanthat
of anyothertypeofdigitalcircuit.
Because thedynamicpowerconsumedduringtheirswitching
transients is proportionaltothesupplyvoltagesquared,it
is
oftendesirabletooperate
CMOS circuitsataslowasupply
voltage as practical. Low voltage operation is particularly useful
wherebatteryoperation
is necessary
such
as
in
implanted
biomedical devices and electronic wristwatches.
For
maximum
immunity
manufacturing
to
tolerances,
enhanced
power-speed
performance,
and
maximum
noise
margins the CMOST threshold voltages must be adjusted to half
the supply voltage. Boron ion implantation is a very flexible and
well controlled technique for threshold voltage adjustment. This
paper will describe the following results for ion implanted low
voltage CMOS integrated circuits:
(a)-A new form for the MOST drain characteristic equation
which includes effects caused by portions of the channel
being
weakly
(rather
than
strongly)
inverted.
These
effectsdominate MOST characteristicswhenthegate
voltage is near
threshold.
The
new
characteristic
equation is essentialforpredictionofdevicebehavior
and transfer curves of CMOS circuits operating from low
supply voltages.
(b)-A fundamental derivation and experimental verification
thattheminimumusablesupplyvoltagefora
CMOS
inverter is about 8 kT/q. This result reveals the attractive
possibility of usingpowersourceswithlowervoltages
and longer shelf life than the common 1.35-V mercury
cell in both medical and watch circuit applications.
(c)-A description of the physical mechanisms by which ion
MOST thresholds.Theaccomimplantedboronadjust
panying theory provides the fundamental basis for the
design of ionimplantedMOSTs.Italsoprovidesa
description of MOS capacitor C-V characteristics which
of implanted MOST
is necessary
for
monitoring
manufacturing processes.
(d)-A
novel,
low
cost,
high
yield
5-mask
process
for
fabricating CMOS integratedcircuits.Thisprocessuses
___
Grove, A.S..“Physics
and Technology of Semiconductor
Devices”. W i l e y ; 1967.
Sze, S.M.. “Physics of Semiconductor Devices”, Wiley; 1969.
Lo, A.W., “Introduction to Digital Electronics”, A d d i s o n W e s l e y ; 1967.
Bauer, L.O., et al, “Ion-Implanted Complementary MOS
Technology,” Wescon, Session 28; Aug., 1971.
standard aluminum gate technology with the addition
of
two low energy boron icn implantations.
MOS transistors
in
low-voltage
digital
circuits
are,
by
necessitv,
alwavs
operating
their
voltages.
. near
- threshold
Unfortunately, in the
vicinity
of
tnrnon
the
assumptions
commonlyusedinderivingdevicecharacteristicequationsare
M O S transislorcharacteristicequationshave
inaccurate.New
been derived which are simple but accurate in the weak inversion
as well aselsewhere.Extendingearlier
regionnearthreshold,
summarized results 12 to the region near threshold it is found
that the drain current
varies exponentially with gate voltage as
( 1 ) ofTable
1 where C o is theoxide
given byequation
capacitance, Cd the bulk depletion region capacitance and
Nfs
the fast surface state density
pereV.Thisequation
is valid as
long as Yb;i< VT + n . L,T/q. For gate voltage VG > V, + n *
kT/q
the
standard
M O S equation
is modified
by
one
additional term showing that the transition into the saturation
region is exponential. For typical device parameters n depends
largely on the fast surface state density Nfs.
Equation ( 1 ) can be used to find the transfer characteristic of
Figure
1 illustrates
the
theoretical
and
a CMOS inverter.
experimental
transfer
characteristics
of a CMOS inverter
operating at low supply voltages for transistors with thresholds
voltages of J7,,
= 0.2 V and VTP = 4 . 2 V. I t is apparent that
the
inverter
retains
good
transfer
characteristics
at
supply
voltages (Vs) as low as 0.3 V.
The transfer Characteristic acalysis shows that the maximum
gain is givenby
equation (2) of Table 1. By imposingthe
requirement that the inverter must have a gain greater than unity
3 one may derive the minimum
t o beusefulindigitalcircuits
usablesupplyvoltage
as givenby
equation (3). For devices
fabricated to minimize Yfs, n/m i s usually in the neighborhood
of two giving Vs,,in
z 0.20 V a t roomtemperature. This is
substantiated by Figure 1.
Thephysicalmechanismsbywhichionimplantedboron
adjuststheP-channelthresholdsareillustratedinFigure
2. If
enoughboron is implanted to shiftthethresholdmorethan
about 0.3 V, the implant achtally creates a P-type region near
the
Sisi02
interface as shown in Figure 2. Pinchoff is
accomplished by depleting the P-type layer from the interface to
a JFET.The device,however,can
thejunction,similarlyto
remain enhancement mode due to interface charge Q s s , and the
metal-semiconductor work function. The threshold shift caused
bytheimplant
is given byequation (4) whcre QrMpL is the
pi is the implanted junction
implanted dose in the silicon and
depth. The second term is the surface band bending required to
deplete the implanted layer. This term must be less than about
0.7 Ti or the surface will invcrt to N-typebeforethedevice
is
pinched off. Thus,there is amaximumchargewhichcanbe
implanted and, therefore, a maximum threshold shift which can
be obtained while still having a device which can
be turned off.
Thcmaximum threslm1.d shift is given byequation (5) where
Authorized licensed use limited to: STMicroelectronics international NV. Downloaded on August 11,2025 at 09:24:33 UTC from IEEE Xplore. Restrictions apply.
A V T , ~is ~ between
~
5
parameters.
V and 10 V for
typical
device
Previously-described
processes
for
low-voltage
implanted
to predeposit the
CMOS circuits use a boron ion implantation
impurity for the P-wells and thereby gain accurate controlof the
is usedfor
N-channel MOST thresholds. A secondimplant
shiftingtheP-channelthreshold.
If theP-wellimplantation is
alsoused for theP-channel MOST sourceanddrainandthe
second implant is used for simultaneous adjustments of P-MOST
and N-MOST threshold voltages, a 5-mask CMOS process results.
In addition to simplicity, this process offers improved powerspeed
performance
reduced
due
to P-MOST
junction
capacitances.
(2)
A =m(e
I mqVS/2nkT
-1) .
V
(3)
VS,rnin
Conclusions
Insummary,theprincipalresultspresentedare:atheory
whichdescribesthebehavior
of MOSTs whenoperated in the
CMOS
weakinversionregionnearthresholdasinlowvoltage
circuits; a calculation of the fundamental lower limit on supply
voltage for CMOS circuits; a basic theory of threshold shifting
via ionimplantation;andanew5-mask
CMOS fabrication
process.
'4- n kT for A = 3
mq
V
(5)
AV
T, max
TABLE 1.
wucT
BULK HOLE
7
FIGURE
1-Low
voltage CMOS inverter
transfer
characteristics: ---- experiment;. . . . .theory.
FIGURE 2-Band structure for a boron implanted P-channel
MOS transistor.
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