Roll Number:
Thapar Institute of Engineering and Technology, Patiala
Electronics and Communication Engineering Department
BE (Semester VI) Mid Semester Test
UEC750: MOS Circuit Design
March, 2023
Name of Faculty: Dr. Arun Kumar Chatterjee,
Time: 02 Hours; MM: 25
Dr. Sujit Kumar Patel, Dr. Anil Singh,
Dr.Rajneesh Kumar
Note: Attempt all questions. Assume any missing data appropriately, if required.
Q.1(a) A p-channel MOS transistor was fabricated on a n-type silicon substrate with a doping
concentration ND = 2 x 1016 cm-3, n-type polysilicon-gate with fermi-potential 0.58V,
(4)
oxide charge density (N0x) is equal to 5x 1010 cm-2 and gate oxide thickness is
0.1 pm. Determine the surface potential and threshold voltage at room temperature for
Vsg = 0 V. Use Est= 11.7 XE0 , Eox= 3.97 xEo, permittivity of free space is 8.854 x
10-14 F Ian, thermal voltage, —
kr = 0.026 V at room temperature and intrinsic carrier
a
concentration is 1.45 x 101° CM-3.
Q.1(b) An n-channel MOS transistor has process parameters len = 110 µA/V 2, fermi-potential
(3)
of the substrate is — 0.3 V, body bias-coefficient is 0.1 V1/2 and Vrom = 0.8 V.
Determine the device current for the following biasing conditions
i. VD = 5 V, Vs = 1 V, VG = 2.5 V, VB = 1 V and aspect ratio is 5.
ii. VD = 5 V, Vs = 2 V, VG = 3 V, VB = 2.5 V and aspect ratio is 2.
Q. 2(a) Show mathematically how threshold voltage, gate oxide capacitance per unit area,
(2)
power density and drain current are effected in terms of scaling factor, S ( where S>1)
for constant electric-filed scaling.
Q 2(b)
Consider an n-channel MOSFET with a substrate doping concentration of Na = 2 x1016
cm-3, a threshold voltage VT = 0.4 V, and a channel length L = 1 gm. The device is
biased with VGs =1 V and Vps = 2.5 V. Determine the ratio of drain current (with
channel length modulation) to the ideal current (without channel length modulation).
Change in channel length, AL, is given by
2€., r„ , i
AL = V-- L V Tip + VDs(sat) + AVDs — VOfp + Vas(sat)]
eA T
Where e is an electron charge, es is absolute permittivity of silicon, .2)p is substrate
fermi potential and AVDs is additional drain to source voltage beyond saturation drain to
source voltage VDs(sat)
1/2
(4)
Q 3(a)
Derive an expression for the switching threshold voltage (Vth) of a CMOS inverter.
(3)
Q 3(b)
Consider a CMOS inverter with the following parameters:
VT0,n = 0.48 V, 1.inCox= 102 RA/V2, VT0,p = - 0.46 V, RpCoa = 51.6 µA/V- and VDD = 1.2 V.
(3)
Determine the (Wn/Wp) ratio so that the switching threshold voltage of the inverter is
Vth = 0.5 V. The channel length of both transistors is 4 = 4 = 60 nm.
Q 4(a)
Implement a 3 input XNOR function in CMOS logic circuit style.
(3)
Q 4(b)
Implement following Boolean expression using CMOS transmission gate:
(3)
F(A, B, C) =A+B+C
2/2