Misr International University
Faculty of Engineering
Electronics and Communications Department
Spring 2024
ECE345: VLSI Lab 2
Experiment Title: Current Mirror
Name: Rawan Ashraf 2019/13921
Instructor: Dr. Ibrahim Lotfy
TA: Eng. Esraa Nashaat
Table of Contents
Introduction ................................................................................................................................3
Schematic ...................................................................................................................................4
Basic Operation .......................................................................................................................4
Creating a Symbol for the Schematic...........................................................................................5
Test Bench ..................................................................................................................................5
DC Response ..............................................................................................................................6
Long vs. Short Channel Transistors .............................................................................................6
Expected DC Response Curves ...............................................................................................7
Layout.........................................................................................................................................9
DRC (Design Rule Check) ........................................................................................................ 10
LVS (Layout Versus Schematic) ................................................................................................ 11
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Introduction
A current mirror circuit is an essential building block in analog integrated circuit design. It is
primarily used to replicate (or mirror) a current from one active device to another, maintaining a
consistent current in different parts of a circuit despite variations in voltage or load conditions.
The main purpose of a current mirror is to provide stable current sources or sinks and to ensure
precise control of current, which is crucial in various applications such as biasing transistors,
amplifiers, and other analog circuits.
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Schematic
Basic Operation
A simple current mirror typically consists of two transistors. Here's a brief overview of its
operation:
1. Reference Current (I_ref): A reference current is established through one transistor,
usually by a resistor connected to a power supply. This transistor is often referred to as
the "reference" or "input" transistor.
2. Mirroring: The second transistor, known as the "output" transistor, is connected in such a
way that it attempts to replicate the current flowing through the reference transistor.
Ideally, the current through the output transistor (I_out) is equal to the reference current
(I_ref).
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Creating a Symbol for the Schematic
Test Bench
1. IREF: This is the reference current input pin. A current source is connected to this pin to
establish the reference current (I_ref).
2. VP: This is the positive power supply pin. A voltage source (Vdc) is connected here to
provide the necessary operating voltage for the circuit.
3. GND: This is the ground pin, which serves as the common return path for the current and
voltage sources.
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DC Response
Long vs. Short Channel Transistors
Long-Channel Transistors: Typically have channel lengths that are large compared to the
minimum feature size of the process technology. They exhibit near-ideal behavior with less
influence from short-channel effects such as velocity saturation and drain-induced barrier
lowering (DIBL).
Short-Channel Transistors: Have channel lengths that are close to the minimum feature size.
They are more susceptible to short-channel effects, which can degrade the performance and
accuracy of the current mirror.
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DC Response Curve Analysis: To analyze the DC response curve, we focus on how the output
current (I_out) varies with the reference current (I_ref) for both long-channel and short-channel
transistors.
Test Setup for DC Response Curve
Reference Current Sweep: Sweep the reference current (I_ref) over a range of values.
Measure Output Current: Measure the output current (I_out) for each value of I_ref.
Vary Supply Voltage (V_dc): Optionally, repeat the measurements for different values of the
supply voltage to observe its impact.
Expected DC Response Curves
Long-Channel Transistors
Linear Region:
I_out closely matches I_ref.
The relationship between I_ref and I_out is linear.
High output resistance, which means I_out remains stable despite variations in the output
voltage.
Saturation Region:
As I_ref increases, I_out enters saturation and no longer increases linearly.
High compliance voltage range.
Short-Channel Transistors
Linear Region:
I_out may deviate from I_ref due to short-channel effects.
The relationship between I_ref and I_out is less linear compared to long-channel transistors.
Lower output resistance, leading to greater sensitivity to variations in output voltage.
Saturation Region:
I_out saturates earlier due to short-channel effects like velocity saturation.
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Lower compliance voltage range compared to long-channel transistors.
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Layout
Transistor Placement:
Place matched transistors (M1 and M2) symmetrically to ensure accurate current mirroring.
Use dummy transistors around the main transistors to improve matching and mitigate edge
effects.
Routing:
Connect the gates of M1 and M2 with short, low-resistance paths to minimize parasitic effects.
Use higher metal layers for power (VP) and ground (GND) to reduce resistance and voltage
drops.
Ensure the IREF and output nodes are routed with minimal parasitic resistance and capacitance.
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DRC (Design Rule Check)
Purpose:

Ensures that the physical layout of the
current mirror adheres to the
manufacturing rules specified by the
semiconductor foundry.
Key Points:

Spacing: Checks that the distances
between various layout features (e.g.,
metal traces, transistor gates) meet the
minimum requirements to avoid short
circuits and manufacturing defects.

Width: Verifies that the widths of all
layout features are within specified
limits to ensure reliability and
performance.

Overlap and Enclosure: Ensures that
different layers, such as diffusion and
polysilicon, overlap correctly and are
enclosed properly to form functional transistors.
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LVS (Layout Versus Schematic)
Purpose:

Confirms that the physical layout of the current mirror accurately represents the intended
schematic design.
Key Points:

Device Matching: Ensures that each
transistor in the schematic has a
corresponding and correctly configured
counterpart in the layout.

Connectivity: Verifies that the
electrical connections between
components in the layout match those
in the schematic, ensuring correct
circuit functionality.

Hierarchy: Checks that hierarchical structures are maintained consistently between the
schematic and layout.
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