ASS 2
NAME: ALI ASGHAR KHAN.
R.NO: 1991.
SUBJECT: BASIC INDUSTRIAL ELECTRONICS.
ASSIGNMENT NO: 02.
ASS 2
Instruction Set of 8085:
Instruction and Data Formats:
The various techniques to specify data for instructions are:
1. 8-bit or 16-bit data may be directly given in the instruction itself.
2. The address of the memory location, I/O port or I/O device, where data resides, may be
given in the instruction itself.
3. In some instructions, only one register is specified. The content of the specified register
is one of the operands.
4. Some instructions specify two registers. The contents of the registers are the required
data.
5. In some instructions, data is implied. The most instructions of this type operate on the
content of the accumulator.
Due to different ways of specifying data for instructions, the machine codes of all instructions
are not of the same length. It may 1-byte, 2-byte or 3-byte instruction.
1.
2.
3.
4.
5.
Data transfer instructions.
Arithmetic instructions.
Logical instructions.
Branch control group.
Control instructions.
ASS 2
1. DATA TRANSFER INSTRUCTIONS:
Instructions, which are used to transfer data from one register to another register, from
memory to register and from register to memory. MOV, MVI, LXI, LDI, STA etc. are few
examples.
\
S.NO Instruction Set
1.
MOV r1, r2
[r1] ← [r2]
Explanation
Move the content of the one
register to another
Example
MOV A, B
2.
MOV r, M
[r]←[[H-L]]
Move the content of memory to
register
MOV B, M
3.
MOV M, r
[[H-L]]←[r]
Move the content of register to
memory
MOV M, C
4.
MVI r, data
[r] ←data
Move immediate data to register
MVI
M, 08
5.
LXI rp, data 16
[rp] ←data 16 bits, [rh] ←8 MSBs, [rl]
←8 LSBs of data
Load Register pair immediate
LXI H,
2500H
6.
LDA addr
[A] ←[addr]
Load Accumulator direct
LDA
2400 H
7.
STA Addr
[addr] ←[A]
Store accumulator direct
STA
2000H
8.
LHLD addr
[L] ←[addr], [H] ← [addr + 1 ]
Load H-L pair direct
LHLD
2500H
9.
SHLD addr
[addr] ←[L], [addr +1] ← [H]
Store H-L pair direct
SHLD
2500H
10.
LDAX rp
[A] ←[[rp]]
Load accumulator indirect
LDAX B
11.
STAX rp
[[rp]] ←[A]
Store accumulator indirect
STAX D
12.
XCHG
[H-L] ↔[D-E]
Change the contents of H-L with D-E
pair
ASS 2
2. ARITHMETIC INSTRUCTIONS:
Arithmetic instructions performs the operation like; addition, subtraction, increment and
decimal.
S.NO
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Instruction Set
ADD r
[A] ←[A]+[r]
ADD M
[A] ← [A] + [[H-L]]
ACC r
[A] ← [A] + [r] + [CS]
ADC M
[A] ← [A] + [[H-L]]
[CS]
ADI data
[A] ← [A] + data
ACI data
[A] ← [A] + data +
[CS]
DAD rp
[H-L] ←[H-L] + [rp]
SUB r
[A] ←[A]-[r]
SUB M
[A] ← [A] - [[H-L]]
SBB r
[A] ←[A]-[H-L]] - [CS]
SUI data
[A] ←[A]-data
SBI data
[A] ←[A]-data-[CS]
INR r
[r] ←[r]+1
INR M
[[H-L]] ←[[H-L]]+1
Explanation
Add register to accumulator
Example
ADD K
Add memory to accumulator
ADD K
Add register with carry to accumulator
ACC K
Add memory with carry to accumulator
ADC K
Add immediate data to accumulator
ADI, 55K
Add with carry immediate data to
accumulator
ACI, 55K
Add register paid to H-L pair
DAD K
Subtract register from accumulator
SUB K
Subtract memory from accumulator
SUB K
Subtract memory from accumulator with
borrow
Subtract immediate data from accumulator
SBB K
Subtract immediate data from accumulator
with borrow
Increment register content
XCHG
Increment memory content
INR K
SUI, 55K
INR K
ASS 2
15.
16.
17.
18.
19.
DCR r
[r] ←[r] -1
DCR M
[[H-L]] ← [[H-L]]-1
INX rp
[rp] ←[rp]+1
DCX rp
[rp] ←[rp]-1
DAA
Decrement register content
DCR K
Decrement memory content
DCR K
Increment memory content
INX K
Decrement register pair
DCX K
Decimal adjust accumulator
DAA
3. LOGICAL INSTRUCTIONS:
The instructions in this group perform logical operation such as AND, OR, compare, rotate, etc.
S.NO
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Instruction Set
ANA r
[A] ←[A]∧[r]
ANA M
[A] ←[A]∧[[H-]]
ANI data[A] ← [A] ∧ [data]
ORA r[A] ←[A]∨[r]
ORA M[A] ←[A]∨[[H-L]]
ORI data[A] ← [A] ∨ [data]
XRA r [A] ← [A]∀[r]
XRA M [A] ← [A] ∀ [[H-L]]
XRI data [A] ←[A] ∀ [data]
CMA [A] ←[A]
CMC
[CS] ←[CS]
STC
[CS] ← 1
CMP r
[A]-[r]
CMP M
[A] - [[H-L]]
Explanation
AND register with accumulator
AND memory with accumulator
AND immediate data with accumulator
OR-register with accumulator
OR-memory with accumulator
OR -immediate data with accumulator
XOR register with accumulator
XOR memory with accumulator
XOR immediate data with accumulator
Complement the accumulator
Complement the carry status
Set carry status
Compare register with accumulator
Compare memory with accumulator
ASS 2
15.
16.
17.
18.
19.
CPI data
[A] – data
RLC
[An+1] ←[An], [A0] ←[A7], [CS] ←[A7]
RRC
[A7] ←[A0], [CS] ←[A0], [An] ←[An+1]
RAL
[An+1] ←[An], [CS] ←[A7], [A0] ←[CS]
RAR
[An] ←[An+1], [CS] ←[A0], [A7] ←[CS]
Compare immediate data with
accumulator
Rotate accumulator left
Rotate accumulator right
Rotate accumulator left through carry
Rotate accumulator right through carry
4. Branch Control Group
This group contains the instructions for conditional and unconditional jump, subroutine call and
return, and restart.

Unconditional Jump:
S.NO Instruction Set
1.
JMP addr(label)
[PC] ← Label

Explanation
Unconditional jump: jump to the
instruction specified by the address
Conditional Jump:
S.NO Instruction Set
1.
Jump addr (label)
[PC] ← Label
S.NO Instruction Set
1.
JZ addr (label) [PC] ← address (label)
2.
JNZ addr (label)
[PC] ← address (label)
3.
JC addr (label)
[PC] ← address (label)
4.
JNC addr (label)
[PC] ← address (label)
5.
JP addr (label)
[PC] ← address (label)
Explanation
Conditional jump: jump to the instruction
specified by the address if the specified
condition is fulfilled
Explanation
Jump, if the result is zero
Jump if the result is not zero
Jump if there is a carry
Jump if there is no carry
Jump if result is plus
ASS 2
6.
JM addr (label)
[PC] ← address (label)
JPE addr (label)
[PC] ← address (label)
JPO addr (label)
[PC] ← address (label)
7.
8.

Jump if odd parity
Explanation
Unconditional CALL: Call the subroutine
identified by the address
Conditional CALL:
S.NO Instruction Set
1. CALL addr (label)
[SP]-1] ← [PCH] , [[SP-2] ← [PCL],
[PC] ← addr (label), [SP] ← [SP]-2
S.NO Instruction Set
1.
CC addr(label)
2.
CNC addr (label)
3.
CZ addr (label)
4.
CNZ addr (label)
5.
CP addr (label)
6.
CM addr (label)
7.
CPE addr(label)
8.
CPO addr(label)

Jump if even parity
Unconditional CALL:
S.NO Instruction Set
1.
CALL addr (label)
[SP]-1] ← [PCH] ,[[SP-2] ← [PCL], [SP]
← [SP]-2, [PC] ← addr(label)

Jump if result is minus
Explanation
Unconditional CALL: Call the subroutine
identified by the address if the specified
condition is fulfilled
Explanation
Call subroutine if carry status CS=1
Call subroutine if carry status CS=0
Call Subroutine if the result is zero
Call Subroutine if the result is not zero
Call Subroutine if the result is plus
Call Subroutine if the result is minus
Call subroutine if even parity
Call subroutine if odd parity
Unconditional Return:
S.NO Instruction Set
1.
RET
[PCL] ← [[SP]], [PCH] ← [[SP] + 1],
[SP] ← [SP] + 2
Explanation
Unconditional RET: Return from
subroutine
ASS 2

Conditional Return:
S.NO Instruction Set
1.
RET
[PCL] ← [[SP],
[PCH] ← [[SP] + 1],
[SP] ← [SP] + 2
S.NO Instruction Set
1.
RC
2.
RNC
3.
4.
RZ
RNZ
5.
6.
RP
RM
7.
8.
RPE
RPO

S.NO
1.
Explanation
Conditional RET: Return from subroutine
Explanation
Return from subroutine if carry status is
zero.
Return from subroutine if carry status is
not zero.
Return from subroutine if result is zero.
Return from subroutine if result is not
zero.
Return from subroutine if result is not plus.
Return from subroutine if result is not
minus.
Return from subroutine if even parity.
Return from subroutine if odd parity.
Restart
Instruction Set
RST
[[SP]-1] ← [PCH], [[SP]-2] ← [PCL],
[SP] ← [SP] - 2,
[PC] ← 8 times n
Explanation
Restart is a one word CALL instruction.
The restart instructions and locations are as follows:
S.NO
1.
2.
3.
4.
Instruction
RST 0
RST 1
RST 2
RST 3
Opcode
C7
CF
D7
DF
Restart Locations
0000
0008
0010
0018
ASS 2
5.
6.
7.
8.
RST 4
RST 5
RST 6
RST 7

S.NO
1.
E7
EF
F7
FF
0020
0028
0030
0038
PCHL:
Instruction Set
PCHL
[PC] ← [H-L],
[PCH] ←[H], [PCL] ←[L]
Explanation
Jump address specified by H-L pair
5. CONTROL INSTRUCTION:
This group contains the instructions for input/output ports, stack and machine control.
S.NO
1.
2.
3.
4.
5.
6.
7.
Instruction Set
IN port – address
[A] ← [Port]
OUT port-address
[Port] ← [A]
PUSH rp
[[SP] - 1] ← [rh],
[[SP] - 2] ← [rh],
[SP] ← [SP] – 2
PUSH PSW
[SP]-1] ← [A],
[[SP] -2] ← PSW,
[SP] ← [SP] – 2
POP rp
[rl] ← [ [ SP ] ],
[rh] ← [[SP]+1],
[SP] ← [SP] + 2
HLT
XTHL
[L] ↔ [[SP]],
[H] ↔ [[SP] + 1]
Explanation
Input to accumulator from I/O port
Output from accumulator to I/O port
Push the content of register pair to stack
Push processor word
Pop the content of register pair, which was
saved, from the stack
Halt
Exchange top stack with H-L
ASS 2
8.
9.
10.
11.
12.
SPHL
[H-L] → [SP]
EI
SIM
RIM
NOP
Moves the contents of H-L pair to stack
pointer
Enable Interrupts
Set Interrupts Masks
Read Interrupts Masks
No Operation