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32-bitKoggeStoneAdder

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32-bit Kogge Stone Adder
Article · December 2019
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Siddharth Shashank Kumar
Manipal Academy of Higher Education
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32-Bit Kogge Stone Adder
62- Siddharth Shashank Kumar
(170907522)
Manipal Institute of Technology (MIT)ECE
Karnataka
siddharthshasank@gmail.com
60- Siddhant Viswanath (170907508)
Manipal Institute of Technology (MIT)ECE
Karnataka
sv2599@gmail.com
Abstract—We are in an era of technology where the speed
and area of the VLSI chip are two of the extremely crucial
factors. Gradually the amount of transistors and other elements
(active and passive) are growing in VLSI/ULSI chips. Adders
play a pivotal role in processors. Generally, the faster the
processor provides the instructions to the applications, the faster
the computer operates. A Kogge-Stone adder (KSA) provides
less hardware, less path gate delay, and better speed
performance as compared to the other adders. This project
paper presents a Verilog implementation of a rapid 32-bit
Kogge-Speed adder (KSA) using VIVADO as its primary coding
software.
delay, as the number of bits is increased the path becomes
longer. After extensive research to improve this vast carry
delay path, Weinberg and Smith proposed with the idea of
Propagate (P) and Generate (G) blocks to address the carry
issue. This proposal is now known as carrying Look Ahead
adder (CLA).
Keywords—Kogge-Stone adder (KSA), Ripple Carry
Adder(RCA), Carry Look Ahead Adder (CLA), Parallel Prefix
Adder (PPA)
I. INTRODUCTION
Adder is one of the primary components of a digital
system. Adders are used in microprocessor & signal
processing jobs like filtering, convolution, image and video
compression, object recognition, modulation, etc. Nowadays,
we don’t want to waste our crucial time doing a single task the
same goes for the processors. Nobody would want to have an
electronic device with a slow processor, but how are adders
and processors related? The answer is simple – the better the
adder design technique the faster the processor works.
Someone who is just introduced to electronics might ask a
basic question – What are adders? Adder is any electronic in
which greater than or equal to two bits of data/information can
be added. We measure the speed of processors by the time that
it takes, time taken by the processors are generally the total
propagation delay taken place in the circuit. The greater the
propagation delay the slower the circuit/processor
whereas the converse also being true. We can also conclude
with the above statement that, ‘smaller the propagation delays
the faster the circuit/processor and vice versa’. For high
efficient addition, the propagation delay should be minimum
as possible. Therefore, in this project paper, we would like to
discuss one of the most efficient adders i.e. Kogge-Stone
adder (KSA), its benefits, disadvantages, circuit complexity
and much more. Before diving straight into our topic, let us
discuss the backstory of the necessity of the Kogge-Stone
adder.
II. BACKGROUND
A. Ripple Carry Adder[3]
Ripple Carry adder (RCA) was one of the most basic and
first adder architecture. In RCA the longest path is the carry
Figure 1. Logic Diagram of Propagator and Generator Block
For an n-bit ripple carry adder we obtain 2n+2 gate delays.
Therefore, for a 32-bit ripple carry adder, the delay is 66 gated
delays.
B. Carry Look Ahead Adder
RCAs, in general, have a long circuit delay due to the
presence of many gates in the carry path from the least
significant bit to the most significant bit. In order to minimize
the 2n+2 gate delays, we find Carry Look Ahead Adder
(CLA) to be more attractive. This adder has the benefit of
significantly reduced delay but with the drawback of more
complexed hardware.
Fig 2. 32-bit CLA
C. Parallel Prefix Adder
The Parallel Prefix Adder and Carry Look Ahead Adder both
utilize the 3-stage structure. The delay in CLA is further
resolved by Parallel Prefix Adder. In PPA, the addition is
presented in the expression of Generation (Gi), Propagation
(Pi), Carry (Ci) & Sum (Si).
Si=PiCi-1
IV. SIMULATION
Figure 2. The layout of Parallel Prefix Adder
III. KOGGE-STONE ADDER
The following Kogge-Stone Adder was proposed by Kogge
and Stone. The architecture of Kogge-Stone Adder consists of
three processing circuits namely1)pre-processing,
2)carry and
3)post-processing blocks [1].
The architecture of Kogge-Stone Adder and Carry Look
Ahead Adder is somewhat similar.
REFERENCES
For 1 bit KSA, the requirement is 2 gate delays. The one bit
KSA circuit can be used to associate Pi and Gi that are
generated from the PG circuit.
[1]
P=AiBi
[2]
G=AiBi
Ci=Gi
Figure 3. A Basic Building Block of KSA
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[3]
Lee Mei Xiang, “VLSI Implementation of a Fast Kogge-Stone ParallelPrefix Adder,” et al 2018 J. Phys.: Conf. Ser. 1049 012077
Vishal Galphat, Nitin Lonbale ECE Deptt, SBITM, Betul, M.P, Design
the High-Speed Kogge-Stone Adder by Using MUX, MUX Int. Journal
of Engineering Research and Applications
Pucknell, VLSI Design
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