Digital Logic Structures
Storage elements
Concept of Memory
Chapter 3
Topics for today’s (2/7) lecture
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What is a storage element?
R-S latch
Gated D-latch
Memory
Sequential circuits
Storage Element
 Logic circuit that has input(s), and output(s).
 Can “store” a bit.
 Output does not change, or in other words the previous output has
been stored.
 There is an input combination that can be used to store a bit (or
keep the output unchanged).
 There is an input combination that can be used to change the
output.
Eg.
The following storage element stores a bit (meaning that the output Z
remains unchanged) as long as B=0. When B=1, Z becomes equal to A.
So, this means that to keep a bit value stored or unchanged, B should be
kept logic 0.
A
B
Z
An example Storage Element
Eg.
The following storage element has 2 inputs, and 2 outputs.
The truth table below gives the behavior of this circuit.
S
R
a
b
1
1
unchanged
1
0
0
1
0
1
1
0
0
0
S
a
b
R
R-S Latch
R-S Latch: Simple Storage Element
S
R
a
b
1
1
unchanged
1
0
0
1
0
1
1
0
0
0
Note that a, b can be
either 0 or 1. As long as
S=R=1, a and b stay
unchanged from their
previous value.
This input combination not allowed. Why? Because both outputs will become 1 (not
complements of each other which is desired). Also, if S and R subsequently both become 1
at the same time, the outputs a and b will oscillate, which is also not desired.
Consider the logic circuit below. Complete the table
of values of P and Q (in steady-state) at each step (i)
through (iv) below that occur in sequence.
You are given P = 0, Q = 1, right before step (i).
Practice
Problem
(i) A = B = 1
(ii) A is now changed to 0.
(iii) A is now changed to 1.
(iv) B is now changed to 0.
B
A
P
(i)
(ii)
(iii)
(iv)
P=
P=
P=
P=
Q=
Q=
Q=
Q=
Q
B
A
Practice
Problem
A
B
P
Q
P
Q
Gated D-Latch
Two inputs: D (data) and WE (write enable)
– when WE = 1, latch is set to value of D
• S = NOT(D), R = D
– when WE = 0, latch holds previous value
• S=R=1
Register
A register stores a multi-bit value.
– We use a collection of D-latches, all controlled by a common
WE.
– When WE=1, n-bit value D is written to register.
Memory
• Now that we know how to store bits,
we can build a memory – a logical k × m array of
stored bits.
Address Space:
number of locations
(usually a power of 2)
k = 2n
locations
Addressability:
number of bits per location
(e.g., byte-addressable)
•
•
•
m bits
22 x 3 Memory
address
word select
word WE
input bits
write
enable
address
decoder
output bits
3-14
Practice Problem
A byte addressable memory has 6 address bits. What is the
addressability, address space.
Practice Problem
A team of longhorns is trying to figure out the specifications of an old computer by
observing the results of a sequence of operations:
i.
When they read the base address 0x0 of the memory, they get back a value
0xF0.
ii. When they try to write to the address 0x10000, an error pops up that “Address
is out of range”
iii. They were able to write 0xAD to the address 0xFFFF successfully.
Based on the results above answer the following questions:
a) What is the addressability of the memory in bytes?
b) What is the address space of the memory? (Simplification not necessary)
c) What is the storage size of the memory in bits?
Instapoll