Sigma-Delta Fractional-N Frequency Synthesis Scott Meninger Michael Perrott Massachusetts Institute of Technology June 7, 2004 Copyright © 2004 by Michael H. Perrott All rights reserved. Note: Much of this material is taken from MITOpenCourseWare http://ocw.mit.edu Course: 6.976 Outline Integer-N synthesis Bandwidth constraints Fractional-N synthesis Issue of fractional spurs Σ∆ Fractional-N Synthesis Quantization noise impact on the PLL Recent developments for lowering the impact of quantization noise Conclusions Q&A - Bandwidth Constraints for Integer-N Synthesizers 1/T ref(t) PFD (1/T = 20 MHz) Loop Filter Bandwidth << 1/T Loop Filter out(t) Divider N[k] PFD output has a periodicity of 1/T Loop filter must have a bandwidth << 1/T - 1/T = reference frequency - PFD output pulses must be filtered out and average value extracted Closed loop PLL bandwidth often chosen to be a factor of ten lower than 1/T Bandwidth Versus Frequency Resolution 1/T ref(t) (1/T = 20 MHz) PFD Loop Filter Bandwidth << 1/T Loop Filter out(t) Divider N[k] Sout(f) 91 N[k] 90 1/T out(t) frequency resolution = 1/T 1.80 1.82 GHz Frequency resolution set by reference frequency (1/T) - Higher resolution achieved by lowering 1/T Increasing Resolution in Integer-N Synthesizers 1/T 20 MHz ref(t) 100 (1/T = 200 kHz) PFD Loop Filter Bandwidth << 1/T Loop Filter out(t) Divider N[k] Sout(f) 9001 N[k] 9000 1/T out(t) frequency resolution = 1/T 1.80 1.8002 Use a reference divider to achieve lower 1/T - Leads to a low PLL bandwidth ( < 20 kHz here ) GHz The Issue of Noise 1/T 20 MHz ref(t) 100 (1/T = 200 kHz) PFD Loop Filter Bandwidth << 1/T Loop Filter out(t) Divider N[k] Sout(f) 9001 N[k] 9000 1/T out(t) frequency resolution = 1/T Lower 1/T leads to higher divide value - Increases PFD noise at synthesizer output 1.80 1.8002 GHz Background: Classical Linearized PLL Model PFD-referred Noise S En(f) 0 Φref [k] α f 1/T Φdiv[k] 0 en(t) e(t) Icp π PFD VCO-referred Noise S Φvn(f) -20 dB/dec H(f) v(t) Loop Charge Pump Divider Filter KV f Φvn(t) Φout(t) jf VCO 1 N N[k] Classical PLL model - Predicts impact of PFD and VCO referred noise sources - Does not allow straightforward modeling of impact due to dynamic divide value variations More on this shortly … Background: Classical Linearized PLL Model PFD-referred Noise S En(f) 0 Φref [k] α π Φdiv[k] PFD VCO-referred Noise S Φvn(f) -20 dB/dec f 1/T 0 en(t) e(t) Icp H(f) Loop Charge Pump Divider Filter v(t) KV f Φvn(t) Φout(t) jf VCO 1 N N[k] Parameterizing in terms of G(f) helps visualize the nature (high-pass or low-pass) and gain of the noise transfer functions Parameterized Version of Classical Model PFD-referred Noise S En(f) VCO-referred Noise S Φvn(f) -20 dB/dec 1/T 0 f 0 en(t) fo 2π α N G(f) f Φvn(t) fo 1-G(f) Φnvco(t) Φnpfd(t) Φn(t) Divider Control Φc(t) of Frequency Setting (assume noiseless for now) Φout(t) G(f) represents the PLL closed loop dynamics G(f) is low-pass Nature of noise transfer very easily seen from the parameterized model Modeling PFD Noise Multiplication VCO-referred Noise S Φvn(f) -20 dB/dec 1/T 0 f 0 en(t) f 2 π α N S e n (f) Radians2/Hz PFD-referred Noise S En(f) S Φvn(f) Φvn(t) 0 π α N G(f) fo 1-G(f) Φnvco(t) Φnpfd(t) Φn(t) Divider Control Φc(t) of Frequency Setting (assume noiseless for now) Φout(t) S Φnpfd(f) Radians2/Hz fo (fo)opt f S Φnvco(f) 0 (fo)opt f PFD spectral density multiplied by N2 before influencing PLL output phase noise High divide values high phase noise at low frequencies Fractional-N Frequency Synthesizers ref(t) (1/T = 20 MHz) PFD out(t) Loop Filter 91 Nsd[k] Divider 90 Dithering Modulator N[k] Sout(f) Nsd[k] 91 1/T 90 out(t) frequency resolution << 1/T 1.80 1.82 Break constraint that divide value be integer Want high 1/T to allow a high PLL bandwidth GHz - Dither divide value dynamically to achieve fractional values - Frequency resolution is now arbitrary regardless of 1/T Classical Fractional-N Synthesizer Architecture ref(t) PFD div(t) frac[k] Accumulator e(t) Loop Filter out(t) N/N+1 1-bit carry_out[k] Nsd[k] = N + frac[k] Use an accumulator to perform dithering operation - Fractional input value fed into accumulator - Carry out bit of accumulator fed into divider Accumulator Operation clk(t) frac[k] M-bit Accumulator M-bit 1-bit residue[k] carry_out[k] residue[k] frac[k] =.25 carry_out[k] Carry out bit is asserted when accumulator residue reaches or surpasses its full scale value - Accumulator residue increments by input fractional value each clock cycle Fractional-N Synthesizer Signals with N = 4.25 carry_out(t) out(t) div(t) ref(t) e(t) phase error(t) Divide value set at N = 4 most of the time - Resulting frequency offset causes phase error to accumulate - Reset phase error by “swallowing” a VCO cycle Achieved by dividing by 5 every 4 reference cycles The Issue of Spurious Tones ref(t) PFD div(t) frac[k] Accumulator e(t) Loop Filter out(t) N/N+1 1-bit carry_out[k] Nsd[k] = N + frac[k] PFD error is periodic - Note that actual PFD waveform is series of pulses – the sawtooth waveform represents pulse width values over time Periodic error signal creates spurious tones in synthesizer output - Ruins noise performance of synthesizer The Phase Interpolation Technique e(t) ref(t) Loop Filter PFD div(t) out(t) N/N+1 α D/A frac[k] M-bit Accumulator residue[k] M-bit 1-bit carry_out[k] Phase error due to fractional technique is predicted by the instantaneous residue of the accumulator - Cancel out phase error based on accumulator residue The Problem With Phase Interpolation e(t) ref(t) Loop Filter PFD div(t) out(t) N/N+1 α D/A frac[k] M-bit Accumulator residue[k] M-bit 1-bit carry_out[k] Gain matching between PFD error and scaled D/A output must be extremely precise - Any mismatch will lead to spurious tones at PLL output Is There a Better Way? A Better Dithering Method: Sigma-Delta Modulation Time Domain M-bit Input Digital Σ−∆ Modulator Analog Output 1-bit D/A Frequency Domain Digital Input Spectrum Quantization Noise Analog Output Spectrum Input Σ−∆ Sigma-Delta dithers in a manner such that resulting quantization noise is “shaped” to high frequencies Dither The sigma-delta noise shaping analysis assumes a white quantization noise spectrum In order to make the input look “sufficiently exciting” a dither signal can be added to it Dithering methods are directly taken from sigma-delta ADC and DAC design - This makes sense since the synthesizer is really a DAC (digital to phase) - Most common method is to add a random sequence to the LSB’s of the input Sigma-Delta Frequency Synthesizers Fout = M.F Fref Fref ref(t) e(t) Charge PFD Pump Loop Filter v(t) out(t) VCO div(t) Nsd[m] Divider N[m] Σ−∆ Modulator M+1 M Σ−∆ Quantization Noise Riley et. al., JSSC, May 1993 f Use Sigma-Delta modulator rather than accumulator to perform dithering operation - Achieves much better spurious performance than classical fractional-N approach Summary: Sources of Phase Noise in Σ∆ Synthesis fo = 84 kHz -60 PFD-referred noise Parasitic Pole In Digital Σ∆ N[k] Σ∆ Noise Synth Output -80 SΦ out,En -90 (f) -100 -110 -120 -130 Σ−∆ noise SΦ VCO-referred noise SΦ (f) out,vn (f) out,∆Σ -140 -150 fc Spectral Density (dBc/Hz) -70 -160 10 kHz 100 kHz f0 1 MHz Frequency 10 MHz Charge-pump / Phase Detector / Reference Low-pass filtered by PLL, dominant at low offset frequencies VCO High-pass filtered by PLL, dominant at high offset frequencies Σ∆ dithered quantization noise Low-pass filtered by PLL, noise/bandwidth tradeoff exists - 1/T A quick note on the linearized model Parasitic Pole In Digital Σ∆ N[k] Σ∆ Noise Synth Output fc Non-linearities break the assumptions of the linear model - The shaped noise can be “folded down” to lower frequencies due to non-linearities in the synthesizer PFD/Charge-pump design This process is best seen through behavioral simulation A Well Designed Sigma-Delta Synthesizer fo = 84 kHz -60 PFD-referred noise Spectral Density (dBc/Hz) -70 -80 SΦ out,En -90 (f) -100 -110 Σ−∆ noise -120 -130 SΦ VCO-referred noise SΦ (f) out,vn (f) out,∆Σ -140 -150 -160 10 kHz 100 kHz f0 1 MHz Frequency 10 MHz 1/T Order of G(f) is set to equal to the Sigma-Delta order Bandwidth of G(f) is set low enough such that synthesizer noise is dominated by intrinsic PFD and VCO noise - Sigma-Delta noise falls at -20 dB/dec above G(f) bandwidth Impact of Increased PLL Bandwidth fo = 84 kHz fo = 160 kHz -60 PFD-referred noise Spectral Density (dBc/Hz) -70 -80 SΦ out,En -90 (f) -100 -110 Σ−∆ noise -120 -130 SΦ VCO-referred noise SΦ (f) out,vn (f) out,∆Σ -140 -70 -80 -90 PFD-referred noise SΦ out,En (f) Σ−∆ noise -100 SΦ -110 -120 -130 (f) out,∆Σ VCO-referred noise SΦ out,vn (f) -140 -150 -150 -160 10 kHz 100 kHz f0 Spectral Density (dBc/Hz) -60 1 MHz Frequency -160 10 kHz 10 MHz 1/T 100 kHz f0 1 MHz Frequency Allows more PFD noise to pass through Allows more Sigma-Delta noise to pass through Increases suppression of VCO noise 10 MHz 1/T 3 GHz/1.2GHz
