Black Box Tutorial: Importing a Verilog Module
System Generator provides a configuration wizard that makes it easy to associate a VHDL or
Verilog module to a Black Box block. The Configuration Wizard parses the VHDL or Verilog
module that you are trying to import, and automatically constructs a configuration M-function
based on its findings. It then associates the configuration M-function it produces to the Black
Box block in your model. Whether or not you can use the configuration M-function as is
depends on the complexity of the HDL you are importing. Sometimes the configuration Mfunction must be customized by hand to specify details the configuration wizard misses.
This topic explains how to use the black box to import Verilog into a System Generator
design and how to use Vivado Simulator to co-simulate the Verilog module.
1. Create a new folder (Black_box) on the desktop.
2. Create a half adder Verilog file on notepad and save it as half_add.v on the Black_box
folder.
3. Create a full adder Verilog file and save it as full_add.v on the same Black_box
folder.
4. Double click on the System Generator token.
5.
MATLAB & SIMULINK will get open.
6.
From Simulink Library Browser Window click on >File > New > Model— OR—- directly click on
7.
Now one Untitled model window will get open, go to File > Save
•
Save model file as full_addtest
NOTE Browse & go to the (Black_box) folder in which we have saved our Verilog files.
8.
Now go to Simulink Library Browser as shown below,
Goto Xilinx Blockset >Basic Elements > (on right hand side) Select System Generator and Drag
and Drop, System Generator—OR—right click on System Generator> Add to full_addtest i.e.
filename.
9. Add the required gateway in and gateway out to the model.
10. Go to the Simulink Library Browser and add a black box block to this subsystem. The black box is
located in the Xilinx Blockset's Basic Elements library. The Black Box Configuration Wizard is
automatically invoked when a new black box is added to the subsystem. A browser window
appears that lists the Verilog source files that can be associated with the black box. From this
window, select the top -level Verilog file full_add.v. This is illustrated in the figure below:
11. The wizard parses the Verilog to generate a configuration M-function for the black
box. This is a MATLAB script that, among other things, associates the black box to
the Verilog and creates black box ports. Once the function has run, the ports on the
black box match those in the top-level Verilog entity (not including clock and clock
enable ports). This is illustrated below:
12. Configure the Gateway in Block, as to match the Input we are giving to Black Box with the Bit
Structure(No. of Bits, Signed, Unsigned etc.) we have specified in our code.
•
Gateway In, Gateway In1 and Gateway In2 as unsigned with number of bits 1
13. Double click on the black box block. The dialog box shown below appears:
•
•
Select the simulation mode as Vivado Simulator
Click OK
14. Go to the Black_Box folder and double click on full_add_config.m file.
• Add the submodule verilog file to this .m file as shown in below
this_block.addFile('half_add.v');
15. From Simulink Library Browse,
• Pick Simulink > Sources > Constant
• Pick Simulink > Sinks > Scope & connect as shown below
16. Run the simulation by clicking the Simulation Play button.