Sukkur Institute of Business Administration University
Department of Electrical Engineering
ESE-412: Digital System Design Lab
Handout#08:
A 3rd Order Moving Average Filter using Verilog HDL
Instructor: Dr. Safeer Hyder
Name: Muhammad Riaz Ali
CMS: 033-17-0020
Lab Report Rubrics
(Add the points in each column, then add across the bottom row to find the total
score)
S.No
1
2
Criterion
Accuracy
Timing
0.5
0.25
Desired output
Minor
mistakes
Submitted
within the given
time
1 day late
0.125
Critical
mistakes
More than 1
day late
Total
Marks
Verilog code:
Lab Exercises:
Scale the size of the Verilog code to implement 7th order moving average filter and compare
the results with 3rd order moving average filter in terms of noise suppression efficiency
Solution:
2
3
4
Results:
As a result, 7th order filter will remove noise from the sigal more efficiently as compare to 3rd
order signal.
5