Materials Today: Proceedings 62 (2022) 944–949
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Materials Today: Proceedings
journal homepage: www.elsevier.com/locate/matpr
A novel 7-Level symmetric inverter module with less circuit components
V. Thiyagarajan ⇑
Department of Electrical and Electronics Engineering, Sri Sivasubramaniya Nadar College of Engineering, Chennai 603 110, India
a r t i c l e
i n f o
Article history:
Available online 13 April 2022
Keywords:
Multilevel inverter
Symmetric
7-level
THD
Digital Logic Circuit
a b s t r a c t
Multilevel Power Converters (MPCs) have vast potential in power electronics research and development
of DC-AC electrical energy conversion system. MLIs have become an inescapable power electronics device
in various power conversion applications due to the incompatibility of traditional two-level inverters.
MLIs are extremely popular for medium power and high AC voltage applications, and thus predicted to
gather incessant attention in future. This article suggests a novel single-phase symmetric 7-level inverter
suitable for a renewable energy application with an effort to lower the count of switching components
and conducting devices in the path for the flow of current. The proposed symmetric type inverter circuit
could produce 7-level output voltage by using three DC sources and seven power electronic switches. The
suggested inverter structure can be used to generate any number of voltage levels, and it can produce all
output voltage levels (i.e.,+ve,-ve and zero), which significantly reduces the inverter’s total standing voltage. The performance of the suggested 7-level inverter topology was confirmed by simulation results
obtained in MATLAB/Simulink.
Copyright Ó 2022 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the Second International
Conference on Engineering Materials, Metallurgy and Manufacturing.
1. Introduction
Renewable energy resource penetration into the electrical grid
has recently been a hot topic. To address local energy demands,
most countries have begun to install solar panels. To provide
power to the grid and loads, renewable energy resources require
power electronics inverters as an interface. Single-phase multilevel
inverters can help in this area by converting the photovoltaic system’s DC voltage into a sinusoidal AC voltage that can be used by
the grid and loads with fewer harmonics and higher efficiency.
Multilevel inverter (MLI) concept emerges as a noteworthy alternative in medium voltage and high-power industrial drive applications to ascertain its position over conventional inverters [1]. The
important applications of MLIs includes hybrid electric vehicles
(HEVs), induction drive motors (IDMs), renewable energy sources,
active power filer, distributed generation and HVDC power transmission and flexible-AC-transmission system (FACTS) devices [2].
It synthesizes the output voltage in steps from several input DC
voltage sources (DCVSs) and semiconductor switches (SSs)where
the shape of the output voltage resembles the shape closer to that
of a sinusoidal waveform. MLIs have more significant features than
⇑ Corresponding author
E-mail address: thiyagarajanv@ssn.edu.in
conventional two-level inverters which includes improved power
quality, reduced filter requirements, less total harmonics distortion
(THD), minimum electromagnetic interference, lower blocking
voltage on the switching devices, lower switching losses, medium
and high voltages capability [3]. The conventional MLI structures
includes Flying-Capacitor (FC) Clamped MLI, Neutral Point
Clamped (NPC) MLI and Cascaded-H-Bridge (CHB) MLI [4,5]. The
important features of FC-MLI include its modularity and use of single DC-link. NPC-MLI is the most flexible MLI structure suitable for
a wide-ranging regenerative and non-regenerative high voltage
industrial applications. However, this MLI structure possesses
unsymmetrical distribution of switching losses, high filter requirements, lack of modularity and use of large number of power electronic devices at higher output levels. In addition, NPC MLI requires
additional clamping diodes which makes the inverter bulky [6,7].
The FC MLI and NPC MLI have disproportionate voltage balancing
of the series connected power capacitors at the input terminals
and requires complex control at higher output levels. To balance
out the capacitor voltage is the main problem in both FC-MLI
and NPC-MLI, which is why they are limited to only five levels,
are unable to cascade, and the output voltage drops to half of the
input voltage, resulting in very high switching losses and high
switching frequency [8,9]. Generally, NPC-MLI and FC-MLI
structure becomes so complex with increase in the device count
https://doi.org/10.1016/j.matpr.2022.04.078
2214-7853/Copyright Ó 2022 Elsevier Ltd. All rights reserved.
Selection and peer-review under responsibility of the scientific committee of the Second International Conference on Engineering Materials, Metallurgy and Manufacturing.
Materials Today: Proceedings 62 (2022) 944–949
V. Thiyagarajan
ing voltage (TSV) of all SSs in H-bridge is so high that the inverter’s
reliability suffers. The paper [12] presented a single-phase sevenlevel MLI structure with only one DCVS and three capacitors connected in series. It’s a good technique to reduce the number of separate DCVSs by using series-connected capacitors. On the other
hand, the capacitor voltage imbalance issue is very difficult to
address. The improved boost type MLI structure is presented in
[13]. The number of conducting SSs, as well as the number of SSs
in the floating capacitor’s charging path, has been a major source
of concern. Because the charging current is larger for a shorter period of time, SSs with higher current rating are required, which
increase both the cost and losses. In [14], a more effective 7-level
NPC inverter structure was suggested to solve the problem of a larger number of devices in the conducting and charging path. The
suggested topology employs eight SSs and a single capacitor to
achieve a 7-level output voltage. This inverter design necessitates
a greater number of power components, as well as a high voltage
stress on the SSs, limiting medium and high voltage applications.
The topology is not suited for high inductive load situations since
the diode is placed in the primary current path.
The objective of this article is to present a new single-phase
sMLI module to create 7-level with reduced circuit components.
A digital logic circuit based multicarrier PWM technique is implemented to generate the gating pulses to achieve 7-level output
voltage. In addition, the presented MLI circuit reduces the number
of conducting SSs and total standing voltage (TSV) for a higher
number of output levels. This paper is organized as follows: Section 2 presents the operation of the proposed 7-level inverter circuit. Section 3 describes the concept of generating switching
pulses with the implementation of digital logic circuit. The simulation results obtained using MATLAB/Simulink are presented in Section 4 and the conclusion is shown in Section 5.
of different ratings which makes it difficult to implement at higher
levels. Hence, many researchers are working on CHB MLIs which
require multiple independent power sources. CHB-MLIs have
recently gotten a lot of interest since they allow for larger output
voltage by cascading numerous low voltage power cells. In CHBMLI, the required output voltage steps are obtained based on individual CHB units and the magnitude of DCVSs. Modularity, utilization of widespread low-voltage SSs, easy maintenance, and ability
to attain high voltage levels are all properties of CHB MLI. In general, CHB MLIs are divided into two MLI structures: symmetrical
MLI (sMLI) and asymmetrical MLI (asMLI) structures [10]. In sMLI
structure, all DCVSs have the same magnitude in each unit while
they are different in the asMLI structure [11]. When compared to
sMLI, the fundamental goal of asMLI is to generate a greater output
voltage steps with the same number of components. The magnitude of the input DCVSs is the most important component in
asMLI. The following categories describe the many asMLI structures[12].
1) Use of an asymmetric DCVSs rather than a symmetric DCVSs
without affecting the inverter structure.
2) Cascading /extending the basic sMLI structure, consisting of
multiple DCVSs, and then connecting them in series in various asMLI configurations.
3) Asymmetrically increasing the basic unit, which consists of
multiple DCVSs, and then connecting the generated basic
unit in sequence.
However, at higher output levels, the larger number of required
DCVSs and SSs are disadvantageous for both symmetric and asymmetric type CHB MLI structures. Selection of appropriate modulation and control techniques is essential to meet the requirements
of the MLI structures. Switching losses account for a large fraction
of total losses in high-power applications, hence lowering the
switching frequency is critical. Minimizing switching frequency
increases the THD of output waveforms [13]. As a result, the difficulty is to reduce the switching frequency while minimizing THD.
The pulse width modulation (PWM) plays a vital role for superior
performance of the MLI structures which determines the nature
of the output voltage waveform. Some of the conventional modulation techniques used in MLIs includes selective harmonic elimination (SHE) PWM, active harmonic elimination, multi-carrier
PWM and space vector modulation (SVM) techniques [14,15].
Among these, the multi-carrier PWM method is commonly used
as it provides good performance and requires less complex control.
Different modulation strategies that can be used in MLIs with
fewer SSs include phase shift PWM, level shift PWM, phaseopposition disposition PWM, and alternate phase-opposition disposition PWM[5–10].For high voltage and large capacity converters, the phase shifted PWM is an excellent modulation approach.
Because of its strong output harmonic qualities and high bandwidth, it has been widely used in numerous domains of power
electronic technology. Bipolar and unipolar PWM are the two types
of phase shifted PWM. Unipolar PWM has a greater equivalent
switching frequency and lower harmonic content in the output
waveform than bipolar PWM, hence it performs better [12].
Most of the recently presented MLI structures can generate
only + ve output voltage levels. In such cases, an additional Hbridge circuit is used to produce -ve output levels where the addition of all DCVSs increases the voltage stress on the H-bridge circuit components thereby increases the switching losses and
rating of the SSs. An asymmetric type 17-level MLI structure is presented in [1]. This inverter circuit consists of four DCVSs and nine
SSs. A symmetric 7-level inverter circuit is presented in [11]. When
there are many conducting SSs, the presented MLI structure
decreases the number of necessary SSs. Moreover, the total stand-
2. Proposed 7-Level inverter circuit
Fig. 1 shows structure of the presented symmetric 7-level inverter module. This inverter circuit consists of three DCVSs and seven
power SSs connected across the load terminals. During symmetric
operation with the magnitude of all DCVSs are same, the presented
MLI module can create 7-level voltage across the load terminals.
The different output levels obtained during both + ve and -ve
cycle of the presented MLI circuit is shown in Fig. 2.
Fig. 1. Proposed 7-level Inverter Circuit.
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V. Thiyagarajan
Materials Today: Proceedings 62 (2022) 944–949
Fig. 2. Output Levels.
switch pairs should not be turned ON simultaneously:(S1, S2), (S3,
S4), (S4, S5) and (S6, S7).
The inherent ability to create both + ve and -ve levels without
any additional polarity changing circuit is the superiority of the
proposed symmetric 7-level inverter circuit. The zero voltage is
obtained by turning ON the followingSSs:S2, S5 and S7 during + ve
cycle and S1, S3 and S6 during -ve cycle. It is observed that only
three SSs are turned ON at any instant to obtain the required output voltage level. In order to avert the short-circuit, the following
3. Generation of switching signals
The MLI switches must be controlled using the pulse width
modulation (PWM) method. To operate the SSs of the MLI topol946
Materials Today: Proceedings 62 (2022) 944–949
V. Thiyagarajan
the gating signals as shown in Fig. 3. The amplitude of each carrier
waveform can be determined by using the given formula [4]:
V Ci ¼ V m
2i 1
m1
; i ¼ 1; 2; 3; :::;
m1
2
ð1Þ
Where, m is the number of output steps.
The logic gate implementation of the proposed symmetric 7level inverter circuit during + ve and -ve cycle are shown in
Fig. 4 (a) and (b) respectively. It is noticed that the switch S2 will
be turned ON during + ve cycle and turned OFF during -ve cycle.
Similarly, the switch S1 will be turned OFF during + ve cycle and
turned ON during -ve cycle. Here, P1 is the logic HIGH signal during + ve cycle and logic LOW during -ve cycle. Similarly, P2 is the
logic LOW signal during + ve cycle and logic HIGH during -ve cycle.
The logic expression to produce the required switching signals for
each of the SSs in the proposed symmetric 7-level inverter circuit is
given in the equation (2).
Fig. 3. Switching Pulse Generation.
S1 ¼ P 2
S2 ¼ P 1
S3 ¼ AP 1 þ A B P2
ogy, it is necessary to generate the gating pulses by various modulation techniques with fundamental switching frequency and high
switching frequency. Different modulation techniques such as
sinusoidal PWM, space vector PWM and selective harmonic elimination PWM methods are most suitable methods to achieve lesser
switching losses, minimum harmonic distortion and better inverter efficiency. Selective harmonic elimination and nearest level
control are two well-known PWM algorithms for low switching
frequency [15]. In this paper, a simple fundamental switching frequency based pulse width modulation method(PWM) method is
implemented to generate the required gating pulses. For the presented MLI circuit, the maximum number of output levels obtained
across the load is 7 levels i.e., three + ve levels, three -ve levels and
one zero level. Here, three number of constant carrier signals are
compared with a single reference sinusoidal signal to generate
S4 ¼ A B
ð2Þ
S5 ¼ A B P1 þ AP 2
S6 ¼ A B P 1 þ ðAB þ A BÞP2
S7 ¼ ðA þBÞP 1 þ ðA B þ A BÞP2
4. Simulation results
The MATLAB/Simulink model of 7-levelsMLI circuit has been
built to validate the performance of the anticipated MLI structure
for different load values and the load frequency is considered as
50 Hz.The 7-level output voltage can be obtained for the proposed
symmetric inverter circuit with the voltage magnitude V1 = V2 = V3 =Vdc = 75 V. The standing voltage across the SSs S6 and S7 is Vdc. The
Fig. 4. Implementation of Logic Gate Circuit (a) + ve Cycle (b) -ve Cycle.
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Materials Today: Proceedings 62 (2022) 944–949
Table 1
Switching Table – 7 level output voltage.
Output Level
Positive Cycle
0
Vdc
2Vdc
3Vdc
Negative Cycle
Voltage Sources
Switches
Voltage Sources
Switches
0
V1
V1 + V2
V1 + V2 + V3
S2,
S2,
S2,
S2,
0
V2
V2 + V1
V3 + V2 + V1
S1,
S1,
S1,
S1,
S5,
S4,
S3,
S3,
Power factor
0
0.3
0.5
0.8
1
Voltage THD
12.23%
12.23%
12.23%
12.23%
12.23%
S3,
S4,
S5,
S5,
S6
S7
S7
S6
standing voltage is 2Vdc across the SSs S1, S2 andS4. The standing
voltage is 3Vdc across the SSs S3 and S5. Hence, the TSV across
the SSs for the symmetric 7-level inverter is 14Vdc. The switching
table for 7-level symmetric inverter operation is given in Table 1.
The 7-level voltage and current waveforms, and the corresponding voltage THD for the different load power factors are
shown in Fig. 5Fig. 6Fig. 7Fig. 8Fig. 9. The THD values for different
load power-factors are given in Table 2.
Table 2
THD for different load parameters.
Load
200 mH
16 O, 160 mH
26 O, 140 mH
42 O, 100 mH
50 O
S7
S7
S6
S7
Current THD
0.92%
1.40%
1.60%
2.97%
12.23%
Fig. 5. pf = 0 (a) Output waveform (b) THD.
Fig. 6. pf = 0.3 (a) Output waveform (b) THD.
Fig. 7. pf = 0.5 (a) Output waveform (b) THD.
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V. Thiyagarajan
Fig. 8. pf = 0.8 (a) Output waveform(b) THD.
Fig. 9. pf = 1 (a) Output waveform (b) THD.
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5. Conclusion
A novel symmetric 7-level MLI structure with reduced circuit
components is presented in this paper. The presented MLI circuit
decreased the required quantity of SSs, driver circuits, and DCVSs
than other similar MLI structures as it uses only three DCVSs and
seven SSs to create 7-level output voltage. To confirm the flexibility
of the inverter module, simulation results for different load parameters have been presented in this paper.The THD of the voltage
waveform is obtained as 12.23%. However, the THD of the current
waveform varies between 0.92% and 12.23% due to the inductive
nature of the load. The proposed simple 7-level inverter circuit is
an important alternative for the use in single-phase energy conversion systems.
CRediT authorship contribution statement
V. Thiyagarajan: Writing – original draft, Writing – review &
editing, Software, Validation, Methodology.
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared
to influence the work reported in this paper.
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