Imran Chowdhury | Lecture Note | VLSI
VLSI
Very Large Scale Integration
Introduction
Electronic circuits can broadly be categorized into 2 (two)
types: (i) Discrete circuits, (ii) Integrated circuits. Very
large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining millions of
transistors onto a single chip.
The integrated circuits or IC`s are devices used in almost
any electronic device today. The development of
semiconductor technology, and fabrication methods lead
to the invention of Integrated Circuits. Prior to the
invention of the IC, all the equipment for computational
tasks used vacuum tubes for implementation of logic gates
and switches. Vacuum tubes, in nature, are relatively
large, high power consuming devices. For any circuit, the
discrete circuit elements had to be connected manually.
The influence of these factors resulted in rather large and
expensive electronic devices even for the smallest
computational task. Therefore, a computer, five decades
ago was enormous in size and very expensive, and
personal computers were a very distant dream.
Semiconductor based transistors and diodes, which have
higher energy efficiency and microscopic in size, replaced
vacuum tubes and their uses. Hence a large circuit could
be integrated on a small piece of semiconductor material
allowing more sophisticated electronic devices to be
created. Even though the first integrated circuits had only
a small number of transistors in them, at present in an area
of your thumb nail billions of transistors are integrated.
Level of Integration / Integration Complexity:
Depending on the number of gates or transistors per chip,
or level of complexity, the field of chip or IC design can
be categorized into 6 (six) schemes as tabulated below.
Although, according to the definitions of the schemes we
are now in the GSI era, but the term VLSI becomes a
‘name’ and still used to refer the field of IC design.
Scheme
Small Scale Integration (SSI)
Medium Scale Integration (MSI)
Large Scale Integration (LSI)
Very large Scale Integration (VLSI)
Ultra large Scale Integration (ULSI)
Giga Scale Integration (GSI)
#gates/chip
Up to 100
Up to 1,000
Up to 10,000
Over 10k
Over 100k
Over 1Billion
Year
1965
1970
1980
1985
1990
2005
Design Abstraction Levels:
VLSI design abstraction levels refer to the fact that what
level or kind of knowledge is required to be a VLSI design
engineer. The ‘system’ level is the highest level of
abstraction where someone has the knowledge of a system
and its outcome on a macro level without having the
knowledge of underlying components that make the
system. Whereas the ‘device’ level is the lowest level of
design abstraction where someone has the knowledge of
physical design of the most fundamental device of the
system on a micro level. It refers to the fact that a VLSI
design engineer is supposed to have the knowledge of
physical design of transistors which are the fundamental
building block of a chip.
The course will be mainly focused on VLSI Design, with
a brief touch on VLSI Technology. Based on the tasks an
IC needs to do, VLSI design can be categorized into 3
(three) branches: (a) Analog VLSI Design (b) Digital
VLSI Design, and (c) Mixed Signal VLSI Design. This
course will be more focused on Digital VLSI Design.
Integrated Circuit (IC) or Microchip:
An Integrated Circuit or IC is a network of
interconnected transistors manufactured on a single
semiconductor (typically Si).
In other words, when all the electronic components of a
circuit are housed or confined in a single substance or
body, then the circuit is called Integrated Circuit or IC.
These components can be semiconductor-based
transistors, diodes, or any other electronic components e.g.
resistors, capacitors.
A Microchip or Chip is not necessarily but sometimes
referred to the ICs those are effectively made up of only
semiconductor-based components e.g. transistors.
Fig: Design abstraction levels of VLSI.
Role of a VLSI Engineer:
The field of VLSI can be broadly categorised into 2 (two)
branches:
1) VLSI Design
2) VLSI Technology
Both branches have their set of engineers responsible for
different set of tasks. Broadly, VLSI Design engineers are
responsible for designing the chip, and VLSI Technology
engineers are responsible for fabricating or manufacturing
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Imran Chowdhury | Lecture Note | VLSI
the chip. VLSI Design engineers can be categorised into 2
(two) types:
a) Front-end VLSI Design Engineers
b) Back-end VLSI Design Engineers
Front-end VLSI Design engineers are responsible for
designing the system (e.g. circuits), defining the functions
and behaviour of the system, defining the architecture of
the system, and synthesizing the design to verify it, etc.
before starting the physical design.
Back-end VLSI Design engineers are responsible for
designing the physical layout of the chip (sometimes
including pad frames), performing post-layout simulation,
placement and routing, etc.
IC Packaging:
Each of the broader categories have numerous types of
sub-categories of packages based on the application and
types of PCBs. But in academics, most commonly we will
encounter only 2 (two) types of IC packages which are
Dual in-line Packages (DIP) and Quadruple in-line
Packages (QIP) as shown below, those falls into the
‘Through-Hole Mount’ category. Some of the other subcategories of IC packages are depicted below as well.
Fig: Dual in-line Packages
(DIP).
Fig: Quadruple in-line
Packages (QIP).
Integrated Circuit Packaging refers to the encasing of a
semiconductor component. The package is a case that
surrounds the circuit material to protect it from corrosion
or physical damage and allow mounting of the electrical
contacts connecting it to the printed circuit board (PCB).
Importance of IC Packaging:
The packaging of an integrated circuit is as important as
the integrated circuit, the semiconductor device within.
The packaging mainly serves 3 (three) purposes:
–
–
–
First, it protects the semiconductor circuit from
physical impairment or damage.
Secondly, it protects the circuit from corrosion.
Finally and most important, it decides how electrical
contacts are laid out from the semiconductor device
over a PCB. This is an important consideration for
both IC designing as well as PCB designing. Like how
the connections are organized in an IC, how they are
laid out using a standard IC package must be coherent
with the application and various use cases of the
respective IC.
Fig: Small Outline Package (SOP/SOIC/SO).
Fig: Quad Flat Package (QFP).
Types of IC Packaging:
There are many different types of integrated circuits, and
therefore there are different types of IC packaging systems
to consider, as different types of circuit designs will have
different needs when it comes to their outer shell.
Although, most of the ICs come in more than one package.
The classifications of IC packaging is mainly done based
on their mounting style. Some of the most common
broader categories of IC packaging are:
1)
2)
3)
4)
5)
Fig: Quad Flat Non-leaded Package (QFN/LCC).
Through-Hole Mount Packages
Surface Mount Packaging
Flat Packages
Ball Grid Array
Chip-Scale Packages
Fig: Ball Grid Array Package (BGA).
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Imran Chowdhury | Lecture Note | VLSI
Fig: Chip-Scale Packages (CSP).
Inside an IC Package:
Although we call the whole package an integrated circuit
or a chip, but technically that is not the case. If an IC
package is opened, there are several components can be
seen, one of which is the IC or chip.
Fig: Real-life image of inside the packaging of an IC.
IC Layout:
The network in an IC is consisted of different layers like
tubs (n-type or p-type), diffusions (drain and source),
polysilicons (a sandwich of polycrystalline silicon and
SiO2), metals (interconnections), contacts (vias), etc. in
three dimension. The geometry of the area-patterns of this
network of layers is known as the IC layout or chip layout.
Connections from the chip to the outside world are made
around the edge of the chip.
In other words, chip layout or IC layout is the
representation of an integrated circuit in terms of planar
geometric shapes which correspond to the patterns of
metal, oxide, or semiconductor layers that make up the
components of the integrated circuit.
Fig: Block diagram of inside the packaging of an IC or Chip.
Chip: The chip is the rectangular semiconductor die sit at
the middle of the package that contains the entire
integrated circuits.
Cavity: It is the rectangular well at the middle of the
package that holds the chip sturdy.
Leads: These are also called pins which are used to mount
and make contacts with a PCB to connect the outside
electronic components of a circuit to the chip.
Bonding Wires: These are very tiny connecting wires that
connect the leads to the chip’s input/output and power
terminals. Generally bonding wires are made up of gold
for better conductivity.
Fig: IC layout a of a RF receiver for ISM-900M.
Pad Frames: These are the small rectangular contacts
sitting at the edge of the chip. Pad frames are used as vias
in between the bonding wires and chip to protect the chip
from unwanted high current through the leads and bonding
wires. A single part of the pad frame is called a pad. A pad
is made much larger in area than the average width of the
interconnecting metals of the IC, with multiple layers of
metals stack on top of each other for higher thermal
tolerance.
Advantages and Limitations of ICs:
Advantages of ICs:
1. Very small size: Hundred times smaller than the
discrete circuits.
2. Lesser weight: As large number of components can
be packed into a single chip, weight is reduced.
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3. Reduced cost: The mass production technique has
helped to reduce the price.
4. High reliability: Due to absence of soldered
connection, few interconnections and small
temperature rise failure rate is low.
5. Low power requirement: As the size is small, power
consumption is less.
6. Easy replacement: In case of failure, chip can easily
be replaced compared to discrete circuits.
Limitations of ICs:
1. If one component in an IC fails, it means the whole IC
has to be replaced.
2. Since the power requirement is low (generally below
10W) due to small size, ICs are generally not used in
high power applications.
3. It is not possible to fabricate coil-based components
like inductor and transformer inside an IC. Therefore,
they need to be connected externally if required.
4. It is neither convenient nor economical to fabricate
capacitances exceeding 30pF since they are bulky.
Therefore, for higher values of capacitance, discrete
components exterior to IC chip are connected.
Kahng (Bell
Lab)
1960
Robert Noyce
(Fairchild
1061
Semiconductor)
Frank Wanlass
(Fairchild
1963
Semiconductor
Federico
Faggin
1968
(Fairchild
Semiconductor)
Intel
1970
First MOSFET
Start of new
era for
semiconductor
industry
First Commercial
IC
First CMOS logic Started the
gates were
modern IC
invented
design era
Later joined
Silicon-gate
Intel to lead
technology (SGT) first CPU Intel
4004 in 1970.
First
2300 MOS
microprocessor
transistors
(Intel 4004)
9mm process.
History of IC Invention:
Inventor
Year Device/Idea
Fleming
1904
1906
William
Shockley (Bell 1945
Lab)
Bardeen,
Brattain, and
1947
Shockley
(Bell Lab)
Werner Jacobi
1949
(Siemens AG)
Shockley (Bell
1951
Lab)
Geoffrey
Dummer
1952
Jack Kilby
(Texas
Instruments)
July
1958
Robert Noyce
Dec.
(Fairchild
1958
Semiconductor)
Remark
Large
expensive,
Vacuum tube diode
powerVacuum triode
hungry,
unreliable
Semiconductor
replacing vacuum -tube
Driving factor
Point Contact
of growth of
Transistor
the VLSI
technology
Patented first IC
No
containing
commercial
transistor-based 2use reported
stage amplifier.
Practical form
Junction Transistor
of transistor
Proposed to
integrate a variety
of electronic
-components in a
semiconductor
First
semiconductor IC
using 2-transistor Father of IC
Flip-flop with
design
Germanium slice
and gold wires
Fig: Point Contact Transistor in 1947.
Fig: First IC using two-transistor Flip-flop in 1958.
Integrated Circuits The Mayor of
on Silicon
Silicon Valley
Fig: First commercial IC in 1961.
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Integrated Circuits Changed the Computer Industry:
Evaluation of Microprocessors:
Despite their great significance of the early transistors,
they were of large size and could not be moved at will. It
was the integrated circuit that facilitated millions of
transistors to be packed onto a single tiny peach of silicon.
Placing such large numbers of transistors on a single chip
vastly increased the power of a single computer and
lowered its cost considerably. Since the invention of
integrated circuits, the number of transistors that can be
placed on a single chip has been increasing year after year,
shrinking both the size and cost of computers even further
and further enhancing its power. Most electronic devices
today use some form of integrated circuits.
Early Computers:
Fig: Intel 4004 microprocessor with 2300 transistors (1970).
Fig: Babbage Difference Engine (1832). It had 25,000 parts.
Babbage Difference Engine: A difference engine is an
automatic mechanical calculator designed to tabulate
polynomial functions. Most mathematical functions,
including logarithmic and trigonometric functions, can be
approximated by polynomials, so a difference engine can
compute many useful tables of numbers.
Fig: Intel Pentium-4 processor with 42 mill. transistors (2000).
VLSI Design Fundamentals
Moore’s Law:
Moore’s law is not really a law of physics or even a proven
theory in the scientific sense (such as E=MC2). Rather, it
was an ‘empirical relationship’ based on observation and
projection of a historical trend of semiconductor
technology by Gordon E. Moore in 1965 while he was
working at Fairchild Semiconductor. Moore later went on
to co-found Intel Corporation and his observation became
the driving force behind the semiconductor technology
revolution at Intel and elsewhere.
Moore’s Law:
Fig: ENIAC - The first electronic computer (1946).
ENIAC: It stands for Electronic Numerical Integrator
and Computer. It was amongst the earliest electronic
general-purpose computers made. It was Turingcomplete, digital and able to solve a large class of
numerical problems through reprogramming.
The number of transistors per chip would grow double
every 18 months, and the growth would be exponential.
Moore’s 2nd Prediction:
The capital cost of a semiconductor fabrication would
increases exponentially over time.
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The End of Moore’s Law:
Fig: Number of transistors per chip for Intel microprocessors
over the years.
In recent years, Moore’s Law has slowly fallen out of
relevance. The predictions Moore made were related to the
speed of innovation and that speed has slowed, just as
Moore expected. Most recently, semiconductor foundry
(fabrication house) TSMC has announced that it plans to
release chips in 3nm (nanometer) process sometime in
2022. By comparison, the diameter of a single atom
measures somewhere between 0.1 and 0.5 nanometers, so
there is a finite limit to how small a single transistor can
become. Some industry experts have theorized that this
trend will create a shift in the way chips are used; rather
than a one-size-fits-all approach, chips will be used for
highly specialized purposes so that the computing power
can be focused more efficiently.
Renowned theoretical physicist Michio Kaku admits the
fact that the Moores Law is breaking down. According to
him "in about ten years or so, we will see the collapse of
Moore's Law. In fact, already we see a slowing down of
Moore's Law. Computer power simply cannot maintain its
rapid exponential rise using standard silicon technology".
Intel Corporation has admitted this.
Fig: Global smartphone RAM capacity (in MB) over the years
(from GSMArena.com).
Kaku also says that when Moore's law finally collapse by
the end of the next decade, we will simply tweak it a bit
with chip-like computers in three dimensions. He then
says "we may have to go to molecular computers and
perhaps late in the 21st century quantum computers".
Feature Size / Process Technology / Node:
Feature Size is an element of semiconductor chip used to
measure and designate the chip generation at the
fabrication level. It refers to a specific semiconductor
manufacturing process and its design rules. Different
feature size often imply different circuit generations and
architectures. Generally, the smaller the feature size the
smaller the transistor size in the chip, producing higher
number of transistors in a single chip, which are both faster
and more power-efficient.
Fig: Global smartphone NAND Flash capacity (in GB) over
the years (from IEEE).
Importance of Moore’s Law:
Technically, Feature Size is the minimum distance
between the source and drain or channel length of a
MOSFET, which today is measured in nanometers.
Feature Size is also called Process Technology, Process
Node, Technology node, or simply Node.
Moore's Law has been used in the semiconductor industry
to guide long-term planning and to set targets for research
and development, thus functioning to some extent as a
self-fulfilling prophecy. It created a roadmap for the
ubiquity of computer technology, including that in
consumer electronics, artificial intelligence, and
supercomputers. In effect, Moore’s Law also predicted the
increasing affordability and accessibility of computer
technology, as the cost per transistor decreases when there
are more transistors available on a single chip.
Fig: Channel Length = Gate Length – (2 × Diffusion Length).
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Discrepancy in Feature Size Naming Convention:
Most recently, due to various marketing and discrepancies
among foundries, the number has lost the exact meaning it
once held. Recent technology nodes such as 22nm, 16nm,
14nm, and 10nm refer purely to a specific generation of
chips made in a particular technology. It does not
correspond to any channel length. Nevertheless, the
naming convention has stuck and it is what the leading
foundries call their nodes.
Since around 2017 node names have been entirely
overtaken by marketing with some leading-edge foundries
using node names ambiguously to represent slightly
modified processes. Additionally, the size, density, and
performance of the transistors among foundries no longer
matches between foundries. For example, Intel's 10nm is
comparable to TSMC's 7nm and Global Foundries' 12nm
processes, while Intel's 7nm is comparable to other
foundries’ 5nm process.
cannot exploit the features of a given process to a
maximum degree.
Wafer and Die:
Wafer: A wafer (also called a slice or substrate) is a thin
slice of semiconductor material, such as a crystalline
silicon, used in electronics for the fabrication of integrated
circuits. It undergoes many microfabrication processes,
such as doping, ion implantation, etching, thin-film
deposition of various materials, and photolithographic
patterning. Finally, the individual microcircuits are
separated by ‘wafer dicing’ and packaged as an integrated
circuit. Wafer diameter can be of various sizes from 25mm
to 675mm, with various thickness under 1mm.
VLSI Design Rules:
In VLSI, manufacturing processes have their inherent
limitations in accuracy, and so the need of design rules
arises. Design rules are geometric constraints provided by
semiconductor manufacturers and imposed on integrated
circuit (IC) designers to ensure their designs function
properly and can be produced with acceptable yield in as
small area as possible without compromising reliability of
the circuit. Design rules act as an interface or
communication link between the circuit designer and the
process engineer during the manufacturing phase. Design
rules are developed by process engineers based on the
capability of their processes. Design rules are specific to a
particular semiconductor manufacturing process.
Fig: Semiconductor wafer.
There are 2 (two) types of design rules available broadly:
1. Absolute Design Rules (μ-based design rules): In this
approach, the design rules are expressed in absolute
dimensions (e.g. 0.75μm) and therefore can exploit the
features of a given process to a maximum degree. These
rules tend to be more complex especially for deep
submicron. The fundamental unit in the definition of a set
of design rules is the minimum line width, which stands
for the minimum mask dimension that can be safely
transferred to the semiconductor material. Even for the
same minimum dimension, design rules tend to differ from
company to company, and from process to process. Now,
CAD tools allow designs to migrate between compatible
processes.
2. Scalable Design Rules (λ-based design rules): In this
approach, all rules are defined in terms of a single
parameter λ. The rules are so chosen that a design can be
easily ported over a cross section of industrial process,
making the layout portable. Scaling can be easily done by
simply changing the value of λ. The key disadvantage of
this approach is that it is too conservative and hence
Fig: The wafer shown in the VLSI class during my MS at
Texas A&M University – Kingsville, USA.
Die: A die is a small block of semiconductor material, on
which a given functional circuit is fabricated. Typically,
integrated circuits are produced in large batches on a
single wafer of electronic-grade silicon (EGS) or other
semiconductor (such as GaAs). The wafer is cut (“diced”)
into many pieces, each containing one copy of the circuit.
Each of these pieces is called a die. Die size varies from
about 5mm2 to 15mm2.
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Photomasks are also known as Optical Masks or Glass
Masks. Photomasks help with the miniaturization of
computer chips. This is because smaller chips require
highly precise images of their general arrangement, which
is near impossible without a lithographic process.
VLSI Design Styles:
Several design styles can be considered for chip
implementation of specified algorithms or logic functions.
Each design style has its own merits and shortcomings,
and thus a proper choice has to be made by designers in
order to provide the functionality at low cost.
Fig: Semiconductor die.
Photomask:
A photomask is basically a “master template” of an IC
design. A photomask is an opaque plate with holes or
transparencies that allow light to shine through in a
defined pattern. They are commonly used in
photolithography and the production of integrated circuits
(IC). Masks are used to produce the pattern of an IC layout
on a semiconductor wafer. Several masks are used in turn,
each one reproducing a layer of the completed design, and
together they are known as a mask set. A single IC may
contain 5-40 layers, resulting in a need for 5-40 unique
photomasks for every IC.
Fig: Photomask.
Fig: Photomask in IC manufacturing process.
1) Programmable Logic Devices (PLD)
a. Field Programmable Gate Array (FPGA)
b. Gate Array (GA) Design
2) Application-Specific Integrated Circuit (ASIC)
a. Standard Cell-based Design (Semi-custom)
b. Full Custom Design
Field Programmable Gate Array (FPGA): A fieldprogrammable gate array (FPGA) is an integrated circuit
that can be programmed or reprogrammed to the required
functionality or application after manufacturing. A fully
fabricated FPGA chip contains thousands of logic gates or
even more, with programmable interconnects, those are
available to users for their custom hardware programming
to realize desired functionality. This design style provides
a means for fast prototyping and also for cost-effective
chip design, especially for low-volume applications. A
typical FPGA chip consists of I/O buffers, an array of
configurable logic blocks (CLBs), and programmable
interconnect structures. Hardware Description Language
(HDL) like Verilog or VHDL is used as the language of
the programming.
Gate Array (GA) Design: In PLD, GA design comes
after FPGA, although it is not programmable by the users,
but fundamental architectures are almost same. Unlike
FPGA, a GA design needs to be sent to a fabrication house
to manufacture the designed circuits onto the chip. But
unlike ASIC, the manufacturing process of GA is much
shorter and requires only 2 (two) steps. The first phase,
which is based on generic (standard) masks, results in an
array of uncommitted transistors (without any
interconnections) on each GA chip. Then, these
uncommitted chips can be customized later, which is
completed by defining the metal interconnects between
the transistors of the array. In a way, ‘GA design’ falls
under the ‘semi-custom design’ as well.
Standard Cell-based Design: Standard cells are precharacterized cells used in ASIC Design flow as basic
building blocks. The standard cell is also called the
polycell, and the design style is also called semi-custom
design. In this design style, all of the commonly used logic
cells are developed, characterized, and stored in a standard
cell library. A typical library may contain a few hundred
cells including inverters, NAND gates, NOR gates,
complex AOI, OAI gates, D-latches, and flip-flops. Each
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gate type can have multiple implementations to provide
adequate driving capability for different fanouts. For
instance, the inverter gate can have standard size
transistors, double size transistors, and quadruple size
transistors so that the chip designer can choose the proper
size to achieve high circuit speed and layout density.
Full Custom Design: In this design style, the entire mask
design is done anew without use of any library. However,
the development cost of such a design style is becoming
prohibitively high. In real full-custom layout in which the
geometry, orientation and placement of every transistor is
done individually by the designer, design productivity is
usually very low - typically 10 to 20 transistors per day,
per designer. Thus, in digital CMOS VLSI, full-custom
design is rarely used. Exceptions to this include the design
of high-volume products such as memory chips, highperformance microprocessors, etc. For logic chip design,
a good compromise can be achieved by using a
combination of different design styles on the same chip.
VLSI Design Flow:
VLSI design flow can be broadly categorized into two
parts: (i) Front-End design, and (ii) Back-End design.
Front-end and back-end design can also be referred to as
High-level design and Low-level design respectively.
Generally, front-end design includes circuit modeling and
synthesis using schematic capture and Verilog/VHDL. It
also includes design and testing through various custom
and Semi-custom methodologies. The back-end design
comprises of IC layout, cell and library design, its
characterization using specific process technology, and
post-layout simulation.
Each and every step of the VLSI design flow has a
dedicated EDA (Electronic Design Automation) tool that
covers all the aspects related to the specific task perfectly.
And most importantly, almost all the EDA tools can
import and export the different file types to help make a
flexible VLSI design flow that uses multiple tools from
different vendors.
MOS Transistor Technology
The fundamental building block of integrated circuits is
transistor, and for modern VLSI it is MOSFET, to be
specific, enhancement type MOSFET. MOSFET is an
acronym for Metal Oxide Semiconductor Field Effect
Transistor. It is a type of FET (Field Effect Transistor) that
has an insulated metal oxide layer between its gate and
channel. On the contrary, JFETs gate is connected with its
channel. The plus point of the insulated gate is its superior
speed and performance with very little leakage current.
MOS Transistors are built on a silicon substrate. Silicon
which is a group IV material is the eighth most common
element in the universe by mass, but very rarely occurs as
the pure free element in nature. It is most widely
distributed in dusts, sands, planetoids, and planets as
various forms of silicon dioxide (silica) or silicates. It
forms crystal lattice with bonds to four neighbors. Silicon
is a semiconductor. Pure silicon has no free carriers and
conducts poorly. But adding dopants to silicon increases
its conductivity. If a group V material i.e. an extra electron
is added, it forms an n-type semiconductor. If a group III
material i.e. missing electron pattern is formed (hole), the
resulting semiconductor is called a p-type semiconductor.
The MOSFET has 4 (four) terminals Gate, Drain, Source
and Body. However, the body terminal is always
connected with the source terminal. Therefore, we are left
with only three terminals. The MOSFET conducts current
between the source and drain. The path for current
between the source and drain is called a channel. The
MOSFET is a transistor which is a voltage-controlled
current device, in which current at two electrodes ‘drain’
and ‘source’ is controlled by the action of an electric field
at another electrode ‘gate’ having in-between
semiconductor and a very thin metal oxide layer.
MOSFETs are classified into 2 (two) types:
1) Depletion type MOSFET (D-MOSFET)
2) Enhancement type MOSFET (E-MOSFET)
Both MOS transistors are further classified as n-type
named nMOS (or n-channel) and p-type named pMOS (or
p-channel) MOSFETs.
Fig: Typical VLSI design flow (top-down design abstraction).
The Depletion type MOSFETs are doped so that a channel
exists even with zero voltage from gate to source during
manufacturing of the device. Hence the channel always
appears in the device. To control the channel, a negative
voltage is applied to the gate (for an n-channel device),
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depleting the channel, which reduces the current flow
through the device. In essence, the Depletion type
MOSFET is equivalent to a closed (ON) switch, while the
Enhancement type MOSFET does not have the built in
channel and is equivalent to an open (OFF) switch. Due to
the difficulty of turning off the Depletion MOSFET, they
are rarely used.
E-MOSFET (n-type) Fabrication Process:
The aim of this course is not to present a detailed
discussion of silicon fabrication technology, which
deserves separate treatment in a dedicated course. Rather,
the emphasis will be on the general outline of the process
flow and on the interaction of various processing steps.
There are a large number and variety of basic fabrication
steps used in the production of modern integrated circuits.
The same process can be used for the fabrication of nMOS
or pMOS or CMOS devices. The step-by-step procedure
of Enhancement type nMOS fabrication steps are
discussed below:
Fig: n-channel Enhancement type MOSFET (left) and nchannel Depletion type MOSFET (right).
Step 1 (Substrate Doping): The process starts with a
semiconductor wafer of pure silicon (Si), were p-type
impurities (boron, gallium, indium, aluminum, etc.) are
added through diffusion or ion implantation technique to
make it a p-type substrate for the nMOS. The size of such
wafer is about 75-150mm in diameter and 0.4mm in
thickness, and the doping concentration is about 1015/cm3
to 1016/cm3.
Fig: Step 1 – Silicon substrate is being doped p-type.
Fig: p-channel Enhancement type MOSFET (left) and pchannel Depletion type MOSFET (right).
E-MOSFET vs D-MOSFET:
SL E-MOSFET
The type of the MOSFET
where the channel is
01 enhanced or induced using
the gate voltage is known
as E-MOSFET.
There is no channel during
02
its manufacturing.
It is a normally OFF
03
transistor by default.
It does not conduct current
04 when there is no Gate
voltage VGS.
It switches ON with the
05 forward biasing of the
gate.
There is a threshold
06 voltage at which the
MOSFET switches ON.
Applying reverse voltage
does not affect E07
MOSFET since there is no
channel.
Applying the forward
voltage generates and
08
increases the width of the
channel.
D-MOSFET
The type of MOSFET
where the channel depletes
with the gate voltage is
known as depletion or
simply D-MOSFET.
The channel is fabricated
during manufacturing.
It is a normally ON
transistor by default.
It conducts current when
there is no Gate voltage
VGS.
It switches OFF with
reverse biasing of gate.
There is no threshold
voltage for switching ON
the MOSFET.
Step 2 (Oxidization – Thick Oxide): In order to select
the specific area to form gate, source and drain on the
surface of the substrate, the fabrication process goes
through
two
steps
called
oxidization
and
photolithography. Growing a think oxide is a part of
oxidization process, where a layer of SiO2 (silicon
dioxide) typically 1μm thick is grown all over the surface
of the wafer to protect it. It is done by heating the silicon
substrate at around 900℃ and sending water vapor onto it.
Fig: Step 2 – Thick oxide layer grown onto silicon substrate.
Step 3 (Photolithography – Photoresist): The surface is
now covered to photoresist which is deposited onto the
wafer and spun to an even distribution of the required
thickness. Which is done by pouring liquid photoresist
onto the surface of the substrate and spinning it.
Applying reverse voltage
to the gate reduces the
channel width.
Applying forward voltage
to the gate increases the
channel width.
Fig: Step 3 – Photoresist deposited onto the surface on top of
the thick oxide layer.
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Step 4 (Photolithography – Masking): The photoresist
layer is then exposed to ultraviolet (UV) light through
photomask, which defines those regions into which
diffusion is to take place. Here negative photoresist is used
which gets harden when exposed to UV light, and remain
soften where it is not exposed to UV light. The black
potion of the photomask or optical mask means closed
section and yellow portions mean open section where UV
light can go through. So, the photoresist under the black
portion will remain soften while the photoresist under the
yellow portions will get harden.
Step 6 (Thin Oxide): A thin layer of SiO2 typically 0.1μm
thick or less is grown all over the surface of the wafer to
make the insulation layer between the polysilicon and
silicon substrate. It is done by heating the silicon substrate
at around 1200℃ and sending oxygen gas or water vapor
onto it. The thickness of the thin oxide layer can be
controlled by the temperature and the reaction time.
Fig: Step 6 – Thin oxide layer gown onto the surface of the
entire wafer.
Fig: Step 4 – Photoresist being exposed to UV light through
patterned photomask.
Step 5 (Etching): These areas are subsequently readily
etched away together with photoresist and underlying
thick oxide so that the surface of the silicon substrate is
exposed to the window defined by the mask. The soften
photoresist is removed by using some kind of solvent to
wash it away. So, the harden photoresist area remains. The
exposed thick oxide layer is removed by pouring
hydrofluoric acid all over the surface. The harden
photoresist areas act as a protective layer so the underlying
thick oxide layer remains. After mixing with the thick
oxide layer, the hydrofluoric acid gets converted into
hydrofluorosilicic acid which can be easily washed away.
Using some other kind of solvent, the remaining harden
photoresist areas are removed as well. The thick oxide
layer outside the window remains.
Fig: Step 5a – The soften photoresist area is being etched away
by using some solvent.
Fig: Step 5b – The thick oxide layer in the window is being
etched away by hydrofluoric acid, and the remaining
harden photoresist areas are being etched away by using
some solvent.
Step 7 (Poly Formation): Polysilicon is deposited using
chemical vapor deposition (CVD) method on top of the
thin oxide layer in the window to form the gate structure.
The polysilicon is basically heavily doped silicon which is
as good as a conductor. The thickness of this polysilicon
layer is typically 1-2μm.
Fig: Step 7 – Polysilicon is being deposited on top of the thin
oxide layer in the window.
Step 8 (Exposing Drain and Source Region): After
forming the gate structure, the silicon substrate needs to be
exposed again exactly where the drain and source are to be
formed, using photolithography (applying photoresist and
exposed to UV lights) and etching (removing photoresist
and oxide layer).
Fig: Step 8 – Drain and source regions are being exposed using
photolithography and etching.
Step 9 (Drain and Source Formation): After exposing
the regions where drain and source are to be formed, the
regions are then doped with n-type impurities using either
diffusion or ion implantation method. Diffusion involves
placing the semiconductor wafer in a high temperature
gaseous atmosphere called ‘diffusion furnace’ containing
the desired impurity, where the doping occurs based on
concentration gradient. Ion implantation generally takes
place at a lower temperature than diffusion, where a beam
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of impurity ions is accelerated and then directed to the
surface of the semiconductor wafer to make the desired ntype regions. Depth of the drain and source doping is
generally 1μm. In this process the polysilicon with
underlying thin oxide and the thick oxide acts as the mask
during formation of drain and source, hence the process is
called self-aligning.
Fig: Step 9 – Drain and source regions are being formed either
by diffusion or ion implantation.
Step 10 (Contact Patterning): After forming the gate,
drain and source region, the area on top of them needs to
be exposed where the metal contacts are to be formed,
using oxidization (adding thick oxide), photolithography
(applying photoresist and exposed to UV lights) and
etching (removing photoresist and oxide layer).
Fig: Step 10 – Contact regions are being patterned using
oxidization, photolithography and etching.
Step 11 (Metallization): After forming the contact cuts,
the whole wafer then has metal (e.g. Aluminum) deposited
over its surface to a thickness typically of 1μm. This metal
layer then goes through photolithography (applying
photoresist and exposed to UV lights) and etching
(removing photoresist and metal layer).to form the
required contact pattern.
doping levels and thickness of the oxide layer. The
operation or working principle of an E-MOSFET (n-type)
can be divided into 4 (four) modes:
1)
2)
3)
4)
Accumulation Mode
Depletion Mode
Weak Inversion Mode
Strong Inversion Mode
1) Accumulation Mode: If the applied gate voltage w.r.t.
body is less than zero or negative ( 𝑉𝑔 < 0 ), negative
charge or electrons will be piled up at the polysilicon gate
and positive charge or holes will be piled up at the bodyterminal. This potential difference across the gate and
body will create an electromagnetic field resulting the
majority carrier holes to be attracted towards the gate and
the minority carrier electrons to be attracted towards the
body-terminal. This way, only the majority carrier holes
get accumulated right beneath the dielectric layer.
Fig: Accumulation-mode operation of an n-type E-MOSFET.
2) Depletion Mode: If the applied gate voltage w.r.t. body
is greater than zero but less than threshold voltage (0 <
𝑉𝑔 < 𝑉𝑇 ), small amount of positive charge or holes will be
piled up at the polysilicon gate and negative charge or
electron will be piled up at the body-terminal. This
potential difference across the gate and body will create an
electromagnetic field resulting the majority carrier holes
to be repelled by the gate potential towards the body. This
way, the majority carrier holes right beneath the dielectric
layer get depleted.
Fig: Step 11 – Metal contacts are being formed using
metallization, photolithography and etching.
E-MOSFET’s Modes of Operation:
The Enhancement type MOSFETs do not have the in-built
channel. By applying the required potentials at the gate,
the channel can be formed. Also for the MOS devices,
there is a threshold voltage (VT), below which not enough
charges will be attracted for the channel to be formed. This
threshold voltage for a MOS transistor is a function of
Fig: Depletion-mode operation of an n-type E-MOSFET.
3) Weak Inversion Mode: If the applied gate voltage
w.r.t. body is slightly greater than threshold voltage (𝑉𝑔 >
𝑉𝑇 ), positive charge or holes will be piled up at the
polysilicon gate and negative charge or electron will be
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Imran Chowdhury | Lecture Note | VLSI
piled up at the body-terminal. This potential difference
across the gate and body will create an electromagnetic
field resulting the majority carrier holes to be repelled by
the gate potential towards the body and the minority
carrier electrons to be attracted towards the gate. This way,
a weak inversion region of electrons is created right
beneath the dielectric layer on top of a still remaining
small depletion region.
When VS > VB, the depletion width of the p-n junction
increases. That makes it more difficult to create a channel
with the same VGS, effectively reducing the channel depth.
In order to return to the same channel depth, VGS needs to
increase accordingly.
The body effect can be seen as a change in threshold
voltage and it is modeled as just that:



Fig: Weak Inversion-mode operation of an n-type E-MOSFET.
4) Strong Inversion Mode: If the applied gate voltage
w.r.t. body is sufficiently greater than threshold voltage
(𝑉𝑔 ≫ 𝑉𝑇 ), the MOS structure turns into strong inversion
region by filling up the remaining depletion region with
more minority carrier electrons. Strong inversion occurs
when the electron concentration at the surface is higher
than the doping concentration in the bulk of the material.
Body Effect of MOSFET:
A transistor is a 4-terminal device. Gate, drain and source
are the 3 terminals that are used to control the transistor,
but the bulk or body, if not properly biased, may put the
transistor inoperable.
VT0n = threshold voltage when VSB = 0.
2ϕf = surface potential (2ϕf ≈ 0.6V for NMOS and
0.75V for PMOS).
γ = body-effect parameter (γ ≈ 0.4V1/2 for NMOS and
−0.5V1/2 for PMOS).
For PMOS, the bulk voltage should always be higher than
the source because the p-n junction is in the opposite
direction (source p+ and bulk n−). Then, the threshold
voltage should be rewritten as:
Digital Logic Families
(IC Design Technologies)
Almost all electronic gadgets make use of different digital
systems for their operation. All the digital systems use
some kind of digital ICs. For the sake of simplicity in
design and compatibility in constructing any complex
digital system, all digital circuits (ICs) used in the design
process should be from same logic family. Besides, for the
expansion of the system, it is necessary to connect
different logic circuits together. In order to connect the
output of one logic circuit to the input of another logic
circuit, one must have circuits with similar characteristics.
Logic Family/Technology
According to the above figure, the p-n junctions defined
by source-bulk and drain-bulk, which are basically two
diodes, must be reverse-biased to stop them from leaking
current from the source/drain to the substrate. That means
that the source potential must always be equal or greater
than the bulk potential. Since drain voltage is always
greater or equal than source voltage, we don't even
consider the drain-bulk junction.
A group of compatible logic circuits having same logic
levels, supply voltages, and electrical characteristics
fabricated on a single IC for performing various logical
functions are referred to as logic family.
According to the components used to make a logic circuit
and as per the construction of the basic logic circuits, there
are different types of logic families. Broadly, logic
families are categorized into 3 (three) types:
1) Bipolar Logic Family
2) Unipolar or MOS Logic Family
3) BiCMOS
Bipolar Logic Family is further categorized into 2 types:
a) Saturated Bipolar Logic Family
b) Non-saturated Bipolar Logic Family
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Saturated Bipolar Logic Family is further categorized into
7 (seven) types:
i.
ii.
iii.
iv.
v.
vi.
vii.
Diode Logic (DL) or Diode-Resistor Logic (DRL)
Resistor-Transistor Logic (RTL)
Direct Coupled Transistor Logic (DCTL)
Integrated Injection Logic (IIL or I2L)
Diode-Transistor Logic (DTL)
High Threshold Logic (HTL)
Transistor-Transistor Logic (TTL)
Non-saturated Bipolar Logic Family is further categorized
into 2 (two) types:
i. Schottky TTL
ii. Emitter Coupled Logic (ECL)
from logic 1 to 0. The average value of THL and TLH is
considered as the propagation delay (TP). The delay times
are measured in between the 50% voltage levels of input
and output wave forms.
𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦, 𝑇𝑃 =
𝑇𝑃𝐿𝐻 + 𝑇𝑃𝐻𝐿
2
2) Power Dissipation: It is the amount of power that a
digital circuit or IC dissipates. The power dissipated is
determined by the average current that is drawn from the
supply voltage (𝑉𝐶𝐶 ). The average current (𝐼𝐶𝐶(𝑎𝑣𝑔)) is the
average value of the current at LOW gate output (𝐼𝐶𝐶𝐿 ) and
the current at HIGH gate output (𝐼𝐶𝐶𝐻 ).
𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑐𝑢𝑟𝑒𝑛𝑡, 𝐼𝐶𝐶(𝑎𝑣𝑔) =
𝐼𝐶𝐶𝐻 + 𝐼𝐶𝐶𝐿
2
Unipolar or MOS Logic Family is further categorized
into 3 (three) types:
𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛, 𝑃𝑑 = 𝑉𝐶𝐶 × 𝐼𝐶𝐶(𝑎𝑣𝑔)
a) pMOS Logic Family
b) nMOS Logic Family
c) CMOS Logic Family
If there are ‘n’ number of logic gates, then the powwr
dissipation per logic gate would be:
Characteristics of Digital IC:
Different logic families possess different characteristic.
One family may be best suited to one situation whereas
another family in some other situation. For example in
certain cases, low power consumption may be the prime
requirement whereas in some other cases it is speed.
Along with power consumption and speed, digital ICs
have other characteristics as well, which are:
1)
2)
3)
4)
5)
6)
7)
8)
Propagation Delay / Operating Speed
Power Dissipation
Figure of Merit
Fan-In and Fan-Out
Voltage and Current Parameters
Noise Immunity / Noise Margin
Operating Temperature Range
Power Supply Requirements
1) Propagation Delay / Operating Speed: Propagation
Delay is the time interval between the application of the
input pulse and the occurrence of the output. If the
propagation delay is less, then the operating speed at
which the IC operates will be faster.
𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛 𝑝𝑒𝑟 𝑔𝑎𝑡𝑒, 𝑃𝑑𝑛 =
𝑉𝐶𝐶 × 𝐼𝐶𝐶(𝑎𝑣𝑔)
𝑛
3) Figure of Merit: In digital logic circuits, a trade-off
exists between power dissipation and the speed. That is,
for higher speed, the power dissipation will be more. For
an efficient operation of any device, achieving a higher
speed with less power dissipation is desirable but a highly
challenging task.
The figure of merit or Speed Power Product is a common
means of measuring the performance of circuits in the
digital logic family.
𝐹𝑖𝑔𝑢𝑟𝑒 𝑜𝑓 𝑀𝑒𝑟𝑖𝑡 = 𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦 × 𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛
To achieve higher performance, the value of figure of
merit should be as low as possible.
4) Fan-In and Fan-Out: Fan-in is the number of inputs
connected to the gate without any degradation in the
voltage level. For the example given in the figure below,
the EX-OR gate has three inputs. So fan-in for the given
EX-OR gate is 3.
Let TPLH is the time delay when the output changes from
logic 0 to 1, and TPHL is the delay when the output changes
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Fan-out refers to the number of inputs that is driven by the
output of another logic gates without any degradation in
the voltage level and keeping the proper function. For
example, the following circuit has an EX-OR gate, which
drives 4 NOT gates. So fan-out of EX-OR gate is 4.
Fan-out is calculated from the amount of current available
in the output of a gate and the amount of current needed in
each input of the connecting gate. It is specified by
manufacturer and is provided in the data sheet.
5) Voltage and Current Parameters: Voltage and
current parameters are defined by the span of input and
output voltage and current. In order to achieve proper
operation in multistage gates or logic circuits, these
parameters should be matched.
Noise Margin at input or output of a gate:
𝐼𝑛𝑝𝑢𝑡 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁(𝑖𝑛) = 𝑉𝐼𝐻(𝑚𝑖𝑛) − 𝑉𝐼𝐿(𝑚𝑎𝑥)
𝑂𝑢𝑡𝑝𝑢𝑡 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁(𝑜𝑢𝑡) = 𝑉𝑂𝐻(𝑚𝑖𝑛) − 𝑉𝑂𝐿(𝑚𝑎𝑥)
𝑉𝑂𝐻(𝑚𝑖𝑛) = 𝑚𝑖𝑛𝑖𝑚𝑢𝑚 𝑂/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 1
𝑉𝑂𝐿(𝑚𝑎𝑥) = 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝑂/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 0
𝑉𝐼𝐻(𝑚𝑖𝑛) = 𝑚𝑖𝑛𝑖𝑚𝑢𝑚 𝐼/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 1
𝑉𝐼𝐿(𝑚𝑎𝑥) = 𝑚𝑎𝑥𝑖𝑚𝑢𝑚 𝐼/𝑃 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑙𝑜𝑔𝑖𝑐 0
𝑉𝑂𝐻 = ℎ𝑖𝑔ℎ 𝑙𝑒𝑣𝑒𝑙 𝑂/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉𝑂𝐿 = 𝑙𝑜𝑤 𝑙𝑒𝑣𝑒𝑙 𝑂/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉𝐼𝐻 = ℎ𝑖𝑔ℎ 𝑙𝑒𝑣𝑒𝑙 𝐼/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉𝐼𝐿 = 𝑙𝑜𝑤 𝑙𝑒𝑣𝑒𝑙 𝐼/𝑃 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
Noise Margin in between two stages of gates:
𝐻𝑖𝑔ℎ 𝑆𝑡𝑎𝑡𝑒 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁𝐻 = 𝑉𝑂𝐻(𝑚𝑖𝑛) − 𝑉𝐼𝐻(𝑚𝑖𝑛)
𝐿𝑜𝑤 𝑆𝑡𝑎𝑡𝑒 𝑁𝑜𝑖𝑠𝑒 𝑀𝑎𝑟𝑔𝑖𝑛, 𝑉𝑁𝐿 = 𝑉𝐼𝐿(𝑚𝑎𝑥) − 𝑉𝑂𝐿(𝑚𝑎𝑥)
7) Operating Temperature Range: All the gates which
are made up of semiconductor devices are temperature
sensitive in nature. The temperature in which the
performance of the IC is effective is called as operating
temperature range. The accepted temperature range for
consumer ICs is from 0℃ to 70℃, from 0℃ to 85℃ for
industrial applications, and from -55℃ to 125℃ for
military applications.
8) Power Supply Requirements: Every IC requires a
certain amount of electrical power to operate, and different
logic family requires a different level of supply voltage.
Usually there is only one power-supply terminal on the
chip and it is marked VCC for bipolar logic family or VDD
for MOS logic family. Obviously low power consumption
is a desirable feature in any digital IC.
Resistor-Transistor Logic (RTL)
6) Noise Immunity / Noise Margin: In digital logic
circuits, the binary values 0 and 1 represent the LOW and
HIGH voltage levels. Due to the interference of the noises,
the voltage levels may increase or decrease. This may lead
to the wrong operation of the device. The noise immunity
is the ability of the logic device to tolerate the noise
without causing spurious change to the output voltage.
Noise margin allows the logic device to function properly
within the specified limits. It is expressed in volts.
RTL is a class of logic circuits built using resistors in the
input network and bipolar junction transistors (BJTs) as
switching devices in output network. The BJTs used in
RTL logic are NPN type. The introduction of the RTL
family revolutionized circuit technology by constructing
the first integrated circuit. RTL was developed for the
Small Scale Integration (≤100 gates) and Medium Scale
Integration (≤1000 gates).
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Imran Chowdhury | Lecture Note | VLSI

This can be cascaded, since there is not much voltage
degradation like DRL.
Disadvantages:
1.
2.
3.
4.
5.
Low fan-out.
Low noise margin.
Slow speed.
High power dissipation.
The input resistances are very high (generally in kΩ)
which are not convenient to fabricate in IC.
Problem 1:
Fig: RTL NAND gate.
(Voltage level: LOW = 0.2V and HIGH = 1V – 3.6V.)


When both inputs are HIGH, both transistors are
ON and act as a short circuit (ideally). Since, the
resistance of short circuit is zero, so the output will be
zero (LOW). But, since practically the voltage drop
across collector and emitter is 0.2V when a BJT is ON,
the output will be actually 0.2V (LOW).
When any one of the inputs is LOW (0.2V), that
transistor connected with the input will be OFF,
making it an open circuit between the output terminal
and ground. Since, the resistance of open circuit is
infinite, the voltage drop across it will be maximum,
and the output will be HIGH.
Design a digital circuit that performs logic NOT (inverter)
operation using RTL, and explain its operation.
Problem 2:
Name the logic gate that the following circuit operates
like. Explain its operation.
Problem 3:
Fig: RTL NOR gate.
(Voltage level: LOW = 0.2V and HIGH = 1V – 3.6V.)


Name the logic gate that the following circuit operates
like. Explain its operation.
When both inputs are LOW (0.2V), both transistors
connected with the inputs are OFF and act as open
circuits. Since, the resistance of open circuit is infinite,
the voltage drop across it will be maximum, and the
output will be HIGH.
When any one of the inputs is HIGH, that transistor
connected with the input will be ON, making it a short
circuit (ideally) between the output terminal and
ground. Since, practically the voltage drop across
collector and emitter is 0.2V when a BJT is ON, the
output will be 0.2V (LOW).
Advantages:

Minimum number of transistors are required to
implement a logic expressions.
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Problem 4:
Name the logic gate that the following circuit operates
like. Explain its operation.

forward biased but D2b will be reversed biased, as they
require 0.7V to turn ON. So, there will be no current
into the base of transistor Q, which means the
transistor is OFF. And, the output at V0 will be HIGH.
When both inputs are HIGH, both input diodes are
reversed biased, and the voltage at point P will be
HIGH. Thus, diode D2a and D2b both will be forward
biased. So, there will be current into the base of
transistor Q, which means the transistor is ON. And,
the output at V0 will be LOW.
Advantages:




Higher fan-out than RTL.
High noise margin than RTL.
Less power consumption than RTL (less resistors).
Higher switching speed than RTL.
Advantages:
1. Lower switching speed than TTL.
2. Higher temperature sensitivity.
3. Large power supply than RTL.
Problem 1:
Diode-Transistor Logic (DTL)
DTL is a class of logic circuits built using diodes in the
input network and bipolar junction transistors (BJTs) as
switching devices in output network. The BJTs used in
RTL logic are NPN type as with RTL. DTL family was
introduced to improve the switching speed over the
circuits of the RTL family. DTL family is the direct
ancestor of TTL family. DTL was developed for the
Medium Scale Integration (≤1000 gates).
Design a digital circuit that performs logic NOT (inverter)
operation using DTL, and explain its operation.
Problem 2:
Name the logic gate that the following circuit operates
like. Explain its operation.
Voltage Parameters of DTL Family
Input HIGH range: 1.9 – 5V
Input LOW range: 0 – 1.1V
Output HIGH range: 2.5 – 5V
Output LOW range: 0 – 0.4V
Problem 3:
Name the logic gate that the following circuit operates
like. Explain its operation.
Fig: NAND gate using DTL logic.

When any one of the inputs is LOW (0.2V), that
input diode is forward biased, and the voltage at point
P will be 0.2V + 0.7V = 0.9V. Thus, diode D2a is
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Transistor-Transistor Logic (TTL)
The Transistor-Transistor Logic (TTL) is a logic family
made up of NPN-type bipolar junction transistors (BJTs).
The basic building block of this logic family is NAND
gate. Inputs of TTL circuit are provided by a multi-emitter
transistor. Number of emitters can be anything based on
the number of inputs. Based on the configuration in output
network, TTL circuits can be 4 (four) types:
1)
2)
3)
4)
TTL with Passive Pull-up
TTL with Active Pull-up (Totem Pole)
TTL with Open Collector Output
TTL with Tristate (Three State) Output
Voltage Parameters of TTL Family
Input HIGH range: 2 – 5V
Input LOW range: 0 – 0.8V
Output HIGH range: 2.4 – 5V
Output LOW range: 0 – 0.4V
1) TTL with Passive Pull-up:
Because of the resistor RC3 in the output network of the
following circuit, it is called TTL with passive pull-up,
since resistors are passive elements.
Problem with Passive Pull-up:
Let’s assume the TTL circuit is driving a capacitive load.
When T3 goes to cut-off, the capacitor will be charged
through RC3. So, the output delay will be dependent on the
time constant RC of the load capacitor. To reduce RC we
will have to reduce R (which is actually RC3), because the
load capacitance is fixed. But reduced RC3 will increase
the collector current of T3 (when it’s ON), which level up
the saturation current point of the transistor. So, to operate
T3 in saturation, current into B3 needs to be higher.
Thus, when T3 is OFF, we need RC3 to be lower; and when
T3 is ON, we need RC3 to be higher. In this circuit, RC3 is
called passive pull-up, and T3 is called active pull-down.
The output impedance of any gate consist of resistive load
and capacitive load. That capacitive load comes from (1)
output capacitance of the output transistor, (2) input
capacitance of gate-based fan outs, (3) stray capacitance
from wiring.
2) TTL with Active Pull-up (Totem Pole):
Because of the transistor T4 in the output network of the
following circuit, it is called TTL with active pull-up,
since transistors are active elements.
Fig: Passive pull-up TTL NAND gate.


When any one of the inputs is LOW (0.2V), the
base-emitter of T1 is forward biased, and the voltage
at point B1 is 0.2V + 0.7V = 0.9V. But the basecollector is reverse biased. So, T1 is ON and will
operate in active region. Therefore, the current into B2
will not be sufficient to turn T2 ON. Since T2 is OFF,
there will be no current into the B3, and T3 will be
OFF. Thus, the output at V0 will be HIGH.
When all the inputs are HIGH, the base-emitter of
T1 is reverse biased, but the base-collector is forward
biased. So, T1 will be in inverted region, and there will
be sufficient current into B2 to turn T2 ON, which inturn provides sufficient current into B3 to turn T3 ON.
Thus, the output at V0 will be LOW.
Advantages:



Higher speed (propagation delay is 1/10 of DTL).
Less power dissipation compared to DTL and RTL
Higher fan-out than DTL and RTL.
Fig: Active pull-up (totem pole output) TTL NAND gate.
When all the inputs are LOW (0.2V), the base-emitter
of T1 is forward biased, and the voltage at point B1 will be
0.2V + VBE1 = 0.2V + 0.7V = 0.9V. But the base-collector
is reverse biased. So, T1 is ON and will operate in the
Active region. Therefore, the current into B2 will not be
sufficient to turn T2 ON, because it requires VB2 = VBE2 +
VBE3 = 0.7 + 0.7 = 1.4V; so at B1 it requires 1.4V + VBC1=
1.4V + 0.7V = 2.1V. Since T2 is OFF, so there will be no
current into the B3, and T3 will be OFF; but T4 will be ON.
Thus, the output at V0 will be HIGH. To be specific,
𝑉0 = 𝑉𝐶𝐶 − 𝐼𝐶4 𝑅𝐶4 − 𝑉𝐶𝐸4(𝑆𝑎𝑡) − 𝑉𝐷
𝑉0 = 5V − 𝐼𝐶4 𝑅𝐶4 − 0.2V − 0.7V ≅ 3.4V
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When all the inputs are HIGH, the base-emitter of T1 is
reverse biased, and the voltage at point B1 will be HIGH.
But the base-collector is forward biased. So, T1 will be in
inverted region, and there will be sufficient current into B2
to turn T2 ON, which in-turn provides sufficient current
into B3 to turn T3 ON; but T4 will be OFF, because VB4 =
VCE2(Sat) + VBE3 = 0.2V + 0.7V = 0.9V, whereas it requires
VBE4 + VD = 0.7 + 0.7 = 1.4V. Thus, the output at V0 will
be LOW, to be specific,
𝑉0 = 𝑉𝐶𝐸3(𝑆𝑎𝑡) = 0.2V
So, in short, active pull-up circuit (T4) provides low
resistance while the T3 is OFF, and while T3 is ON the
active pull-up provides high resistance.
Fig: Open collector TTL with external pull-up resistor.
3) TTL with Open Collector Output:
When the pull-up network at the output stage of TTL is
removed from the supply, it is called TTL with open
collector output, since the collector of the output transistor
T3 is open.
While open collector TTL circuits can be used in this way,
many of the benefits of TTL circuits are lost by
eliminating the active pull-up transistor. To gain back
those advantages and maintain the high speed and superior
noise immunity of TTL circuits, the three-state TTL was
developed.
Applications:



In driving lamps or relays.
In performing wired logic.
In the construction of a common bus system.
4) TTL with Tristate Output:
Fig: Open collector TTL NAND gate.


When any one of the inputs is LOW (0.2V),
according to TTL with passive pull-up, there will be
no current into the B3, and T3 will be OFF. So, the
collector of T3 (output terminal) is disconnected from
ground, and hence the output V0 will be FLOATING.
When all the inputs are HIGH, according to TTL
with passive pull-up, there will be a sufficient current
into the B3 and T3 will be ON. So, the collector of T3
(output terminal) is now connected to the ground, and
hence the output V0 will be LOW. But T3 will not be
in saturation.
Therefore, it is not possible to get a suitable output from
this circuit for either logic input HIGH or LOW. So, when
this circuit is used in an IC, a pull-up resistor RL is placed
externally from the power terminal. The power terminal
could be the same VCC, or it could be a separate supply
with higher voltage even to pull the output level higher.
In normal logic circuits, there are two states of output,
LOW and HIGH, which are called low impedance outputs.
In complex digital systems like microcontrollers and
microprocessors, a number of gate outputs may be
required to connect to a common line, referred to as a ‘bus’
which in turn may be required to drive a number of gate
inputs. When a number of gate outputs are connected to
the bus,


Totem pole TTL outputs leads to heating of the ICs
which may get damaged.
Open-collector TTL outputs causes the problems of
loading and speed of operation.
To overcome these difficulties, in addition to low
impedance outputs (LOW & HIGH), there is a third state
known as the High-impedance (High-Z or Floating) state.
Such TTL circuits in which the output can have three
states is called TTL with Tristate output. When the gate of
such logic circuit is disabled, it is in the third state. A
tristate bus is a computer bus connected to multiple tristate
output devices, only one of which can be enabled at any
point to avoid bus contention. This scheme allows for the
same bus to be shared among multiple devices.
The following circuit is a TTL with tristate output, where
the 3rd state or High-Z state occurs when both T3 and T4
are in the OFF state. In other words,
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

If E (Enable) is LOW, then the output will be in High
Impedance state.
If E (Enable) is HIGH, then the output will be exactly
as an Inverter.
T2 is turned ON. Since T2 is ON, the voltage at B3 is HIGH,
which turns ON T3. Thus, the output at V0 will be LOW.
𝑉0 = 𝑉𝐶𝐸3(𝑆𝑎𝑡) = 0.2V
Now, since the voltage at B4 is VCE2(Sat) + VBE3 = 0.2 + 0.7
= 0.9V which is less than the required voltage VBE4+ VD =
0.7 + 0.7 = 1.4V, both T4 and D will be OFF.
When E is LOW: D1 and D4 are ON. Since D4 is ON or
short-circuited, the voltage at B1 will be LOW (0.2 + VD4
= 0.2 + 0.7 = 0.9V). Now whether the input A is HIGH or
LOW, the voltage at B1 is LOW. Since the voltage at B1
(0.9V) is less than the required voltage (2.1V) to turn ON
D3, it remains OFF which in turn keeps T2 and T3 OFF.
Now, since B4 is connected to E which is LOW, both T4
and D will be OFF as well. Since both T3 and T4 are OFF,
the output will be FLOATING.
Problem 1:
Fig: Tristate TTL Inverter.
Design a digital circuit that performs Inverting operation
using TTL Totem Pole configuration, and explain its
operation.
Problem 2:
Name the logic gate that the following circuit operates
like. Explain its operation.
Fig: Tristate TTL Inverter replacing T 1 with diode equivalents.
When E is HIGH and A is LOW (0.2V): Since E is
HIGH, D1 and D4 are OFF. Since A is LOW, D2 is ON, and
the voltage at B1 will be 0.2V + VD2 = 0.2V + 0.7V = 0.9V.
This keeps D3 OFF since the required voltage for D3 is VD3
+ VBE2 + VBE3 = 0.7 + 0.7 + 0.7 = 2.1V. Since D3 is OFF,
T2 is OFF; and thus voltage at B3 is zero, which keeps T3
OFF as well. Now, since B4 gets HIGH from the supply,
T4 turns ON. Thus, the output at V0 will be HIGH.
Problem 3:
Name the logic gate that the following circuit operates
like. Explain its operation.
𝑉0 = 𝑉𝐶𝐶 − 𝐼𝐶4 𝑅𝐶4 − 𝑉𝐶𝐸4(𝑆𝑎𝑡) − 𝑉𝐷
𝑉0 = 5V − 𝐼𝐶4 𝑅𝐶4 − 0.2V − 0.7V ≅ 3.4V
When E is HIGH and A is HIGH: Since E is HIGH, D1
and D4 are OFF. Since A is HIGH, D2 is OFF; so the
voltage at B1 will be HIGH, which turns D3 ON, and hence
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Problem 4:
Name the logic gate that the following circuit operates
like. Explain its operation.
Fig: Resistive Load nMOS Inverter.
The operation of the above nMOS inverter with resistive
load is same as the general schematic of nMOS inverter
since the load resistor is always ON.
nMOS Logic Family/Technology
nMOS logic family is a class of digital circuits built using
enhancement type n-channel MOSFET in the driver
network and either passive or active element as the load.
In case of passive load, the load is a resistor, and in case
of active load, the load can be either an enhancement (in
active or saturation mode) or depletion type nMOS. nMOS
logic family was introduced to improve the switching
speed over the circuits of the pMOS family, since
electrons in nMOS are fast-moving than holes in pMOS.
nMOS was developed for the Large Scale Integration
(≤10000 gates).
Fig: Saturated Enhancement Load nMOS Inverter.
The operation of the above nMOS inverter with E-MOS
load is same as the general schematic of nMOS inverter
since the load nMOS is always ON and in saturation mode.
It is in saturation mode because according to the load
configuration 𝑉𝐺𝑆 = 𝑉𝐷𝑆 , which satisfies the saturation
condition 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇 .
Fig: A general schematic of nMOS Inverter.
According to the above schematic, considering the load is
ON, if HIGH voltage (logic 1) is applied at 𝑉𝑖𝑛 , the output
at 𝑉𝑜𝑢𝑡 will be LOW (logic 0) since the driver nMOS is
ON. And, if LOW voltage is applied at 𝑉𝑖𝑛 , the output at
𝑉𝑜𝑢𝑡 will be HIGH since the driver nMOS is OFF.
Based on the type and mode (in case of active element) of
load nMOS logic can be categorized into 4 (four) types:
1)
2)
3)
4)
Resistive Load nMOS Logic
Saturated Enhancement Load nMOS Logic
Linear Enhancement Load nMOS Logic
Depletion Load nMOS Logic
Fig: Linear Enhancement Load nMOS Inverter.
The operation of the above nMOS inverter with E-MOS
load is same as the general schematic of nMOS inverter
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since the load nMOS is always ON and in linear mode. It
is in linear mode considering 𝑉𝐺𝑆 is always greater than
𝑉𝐷𝐷 by more than 𝑉𝑇 , which satisfies the linear condition
𝑉𝐷𝑆 ≤ 𝑉𝐺𝑆 − 𝑉𝑇 . Because:
⇒ 𝑉𝐺𝐺 − 𝑉𝐷𝐷 > 𝑉𝑇
⇒ 𝑉𝐺𝑆 − 𝑉𝐷𝑆 > 𝑉𝑇
⇒ −𝑉𝐷𝑆 < 𝑉𝑇 − 𝑉𝐺𝑆
∴ 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇
The Boolean expression for two-input NAND gate is
𝑍 = ̅̅̅̅̅̅
𝐴 ∙ 𝐵 , where the number of inputs are 2 and logic
operation is multiplication. Therefore, the number of
nMOS in the driver network will be 2 and they will be
connected in series.
Ex 2: Two-input NOR Gate using nMOS Logic:
Fig: Depletion Load nMOS Inverter.
The operation of the above nMOS inverter with depletion
load is same as the general schematic of nMOS inverter
since the load D-MOS is always ON, because according to
the load configuration 𝑉𝐺𝑆(𝐿𝑜𝑎𝑑) = 0.
nMOS Combinational Logic Design:
Combinational logic circuits or gates are the basic building
blocks of all digital systems. These circuits perform
Boolean operations on multiple input variables and
determine the outputs as Boolean functions of the inputs.
Designing combinational circuits with nMOS logic
technically means designing the driver (or pull-down)
network, since there is only one (can be any one of the 4)
load in the pull-up network. Though in case of an nMOS
inverter, there is only one nMOS in the driver network as
well, since the number of input of an inverter is one. So
basically, the number of nMOS and their connection in the
driver network depends on the number of inputs and their
Boolean function respectively. The following table shows
the type of connection in the driver network based on the
logic operation in the Boolean function. nMOS logic
works for inverted logic by default.
Logic Operation
Addition
Multiplication
The Boolean expression for two-input NOR gate is
𝑍 = ̅̅̅̅̅̅̅̅
𝐴 + 𝐵, where the number of inputs are 2 and logic
operation is addition. Therefore, the number of nMOS in
the driver network will be 2 and they will be connected in
parallel.
Problem 1:
What is the Boolean expression of the following logic
circuit? Explain its operation.
Driver Network
Parallel
Series
Ex 1: Two-input NAND Gate using nMOS Logic:
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Conventional Static CMOS Logic
Problem 2:
What is the Boolean expression of the following logic
circuit? Explain its operation.
Exercise 1:
Draw the depletion load nMOS logic circuit for the
following Boolean expression, 𝑉𝑜𝑢𝑡 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴(𝐷 + 𝐸) + 𝐵𝐶 .
Solution:
The basic idea for Conventional Static CMOS technology
is to combine n-channel and p-channel MOSFETs such
that there is never a conducting path from the supply
voltage to ground. As a consequence, these logic circuits
consume very little energy. This logic family incorporates
enhancement type nMOS in the pull-down network and
enhancement type pMOS in the pull-up network in equal
numbers. Both n-channel and p-channel MOSFETs are
designed to have matching characteristics. Conventional
Static CMOS technology is simply called CMOS.
Conventional Static CMOS technology is a predominant
technology for manufacturing integrated circuits due to
several key advantages. The main advantage of this
technology over nMOS and BIPOLAR technology is the
much smaller power dissipation. Unlike nMOS or
BIPOLAR circuits, a Static CMOS circuit has almost no
static power dissipation. Power is only dissipated in case
the circuit actually switches. This allows integrating more
Static CMOS gates on an IC than in nMOS or BIPOLAR
technology, resulting in higher performance.
Fig: Static CMOS Inverter.
CMOS Logic Family
(CMOS Technology)
The term CMOS stands for “Complementary Metal Oxide
Semiconductor”. It is a class of digital circuits built using
both enhancement type nMOS and pMOS. The advantages
of CMOS logic family includes high speed, low power
dissipation, high noise margins in both states, and a wide
range of source and input voltages (fixed source voltage).
CMOS logic family was developed for the Very Large
Scale Integration (>10000 gates) and beyond. This logic
family can be classified into the following categories:
1) Static CMOS Logic
a) Conventional Static CMOS Logic
b) Pseudo-nMOS Logic (Ratioed Logic)
c) Pass Transistor & Transmission Gate Logic
2) Dynamic CMOS Logic
a) Domino Logic
b) np-CMOS Logic
According to the above schematic, if HIGH voltage (logic
1) is applied at 𝑉𝑖𝑛 , the pMOS will be OFF and the nMOS
will be ON. Since the nMOS is ON, the resistance between
𝑉𝑜𝑢𝑡 and ground will be ideally zero, and hence the voltage
drop at 𝑉𝑜𝑢𝑡 will be LOW (logic 0). And, if LOW voltage
is applied at 𝑉𝑖𝑛 , the pMOS will be ON and the nMOS will
be OFF. Since the nMOS is OFF, the resistance between
𝑉𝑜𝑢𝑡 and ground will be ideally infinite, and hence the
voltage drop at 𝑉𝑜𝑢𝑡 will be HIGH.
Static CMOS Combinational Logic Design:
The design of Conventional Static CMOS combinational
logic circuits can be based on the basic principles
developed for nMOS logic circuits in the previous section.
In this logic family, n-channel MOSFETs are arranged in
a pull-down network (PDN) between the output and the
ground rail (VSS) while p-channel MOSFETs are in a pullup network (PUN) between the output and the supply
voltage rail (VDD). All the inputs are distributed to both the
PUN and PDN. Thus, an n-channel MOSFET will be ON
when the corresponding p-channel MOSFET is OFF, and
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vice-versa. For any input pattern, one of the networks is
ON and the other is OFF.
Fig: General block diagram of static CMOS logic.
Ex 2: Two-input NOR Gate using Static CMOS:
The Boolean expression for two-input NOR gate is
𝑍 = ̅̅̅̅̅̅̅̅
𝐴 + 𝐵, where the number of inputs are 2 and logic
operation is addition. Therefore, the number of nMOS in
the PDN will be 2 and they will be connected in parallel.
And, the number of pMOS in the PDN will be 2 as well
and they will be connected in series.
Combinational logic circuits perform Boolean operations
on multiple input variables and determine the outputs as
Boolean functions of the inputs. Designing combinational
circuits with Static CMOS logic technically means
designing the pull-down and pull-up network. The number
of nMOS in the PDN and pMOS in the PUN depends on
the number of inputs, and their connection depends on the
Boolean function. The following table shows the type of
connection in the PND and PUN based on the logic
operation in the Boolean function. Like nMOS logic,
Static CMOS logic works for inverted logic by default.
Logic Operation
Addition
Multiplication
Pull-down
Network (PDN)
Parallel
Series
Pull-up
Network (PUN)
Series
Parallel
Ex 1: Two-input NAND Gate using Static CMOS:
Exercise 1:
Draw the Static CMOS logic circuit for a 4-input NAND
̅̅̅̅̅̅̅̅).
gate (𝐹 = 𝐴𝐵𝐶𝐷
Solution:
The Boolean expression for two-input NAND gate is
𝑍 = ̅̅̅̅̅̅
𝐴 ∙ 𝐵 , where the number of inputs are 2 and logic
operation is multiplication. Therefore, the number of
nMOS in the PDN will be 2 and they will be connected in
series. And, the number of pMOS in the PDN will be 2 as
well and they will be connected in parallel.
Exercise 2:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵) · 𝐶 .
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Solution:
Exercise 5:
Draw the Static CMOS logic circuit for the Boolean
(𝐴 + 𝐵 + 𝐶) · 𝐷 .
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Solution:
Exercise 3:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵)(𝐶 + 𝐷).
Solution:
Exercise 6:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐷 + 𝐴(𝐵 + 𝐶).
Solution:
Exercise 4:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵 + 𝐶𝐷.
Solution:
Exercise 7:
Draw the Static CMOS logic circuit for the Boolean
(𝐴 + 𝐵)𝐶 + 𝐷.
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Solution:
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Exercise 8:
Exercise 10:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴(𝐵𝐶 + 𝐷).
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵)(𝐶 + 𝐷)(𝐸 + 𝐹 + 𝐺𝐻).
Solution:
Solution:
Exercise 9:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝑉𝑜𝑢𝑡 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴(𝐷 + 𝐸) + 𝐵𝐶 .
Solution:
Exercise 11:
Draw the Static CMOS logic circuit for the Boolean
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅
𝐴(𝐵 + 𝐶̅ ).
Solution:
Exercise 12:
Draw the Static CMOS logic circuit for the Boolean
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ ).
expression, 𝐹 = 𝐴
+ 𝐵(𝐶̅ + 𝐷
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Solution:
The operation of the above Pseudo-nMOS inverter is same
as an nMOS inverter since the load pMOS is always ON,
because according to the load configuration 𝑉𝐺(𝐿𝑜𝑎𝑑) = 0,
which makes 𝑉𝐺𝑆(𝐿𝑜𝑎𝑑) = −𝑉𝐷𝐷 .
Pseudo-nMOS Combinational Logic Design:
The design of Pseuso-nMOS combinational logic circuits
is similar to the basic principles developed for nMOS logic
circuits in the earlier section, except for the fact that the
load is always a pMOS. So, the structure of driver (or pulldown) network with nMOS, number of nMOS and their
interconnection, input connections, etc. remain same.
Problem 1:
Draw the Static CMOS logic circuit for the Boolean
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅
expression, 𝐹 = 𝐴
+ 𝐵(𝐶
+ 𝐷 ).
Problem 2:
Draw the Static CMOS logic circuit for the Boolean
̅̅̅̅̅̅
expression, 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵(𝐶
∙ 𝐷 ).
Pseudo-nMOS Logic
Although CMOS is superior in terms of static power loss
and operating speed to its predecessor, but it needs more
transistors than others in the same logic family like nMOS
logic. Hence area consumption is more for CMOS. This is
where Pseudo-nMOS logic comes in which is based on
nMOS logic structure keeping the CMOS definition
satisfied by incorporating pMOS load in the nMOS logic
circuit. The advantages of Pseudo-nMOS logic includes
less area consumption, hence low gate capacitance, thus
higher operating speed. But the main disadvantage of this
logic is it carries on the static power loss from nMOS logic
since the load is always ON. Like nMOS logic, PseudonMOS logic was developed for the Large Scale Integration
(≤10000 gates).
Fig: General block diagram of Pseudo-nMOS logic.
Combinational logic circuits perform Boolean operations
on multiple input variables and determine the outputs as
Boolean functions of the inputs. As with nMOS logic,
designing combinational circuits with Pseudo-nMOS
logic technically means designing the driver (or pulldown) network, since there is only one pMOS load in the
pull-up network. Again, as with nMOS logic, the number
of nMOS and their connection in the driver network
depends on the number of inputs and their Boolean
function respectively. The following table shows the type
of connection in the driver network based on the logic
operation in the Boolean function. Like nMOS and CMOS
logic, Pseudo-nMOS works for inverted logic by default.
Logic Operation
Addition
Multiplication
Driver Network or Pulldown Network (PDN)
Parallel
Series
Exercise 1:
Draw the Pseudo-nMOS logic circuit for a 4-input NAND
̅̅̅̅̅̅̅̅).
gate (𝑌 = 𝐴𝐵𝐶𝐷
Solution:
Fig: Pseudo-nMOS Inverter.
Version 9.53 | Page 27 of 36
Imran Chowdhury | Lecture Note | VLSI
voltage can be 0 to 𝑉𝐷𝐷 − 𝑉𝑇𝑛 , since 𝑉𝐺𝑆 needs to be at
least equal to 𝑉𝑇𝑛 (generally 1V) to turn ON the nMOS.
Fig: nMOS Pass Transistor.
Considering the supply voltage 𝑉𝐷𝐷 = 5𝑉 and threshold
voltage 𝑉𝑇𝑛 = 1𝑉 for the nMOS, for different values of
𝑉𝑖𝑛 the values of 𝑉𝑜𝑢𝑡 will be as follows:
𝑉𝐷𝐷 = 5𝑉
𝑉𝑇𝑛 = 1𝑉
𝑽𝒐𝒖𝒕 (V)
𝑽𝒊𝒏 (V)
Exercise 2:
Draw the Pseudo-nMOS logic circuit for a 4-input NOR
gate (𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + 𝐶 + 𝐷).
Solution:


Pass Transistor Logic
Pass Transistor:
Like Pseudo n-MOS logic, Pass Transistor logic comes in
to reduce the number of transistor from a logic circuit that
the CMOS logic circuits encounter. The basic principle of
Pass Transistor is to pass a voltage from one point to
another, and single nMOS or pMOS transistor is the basic
building block of this logic. So, based on the type of
transistor, Pass Transistor can be 2 (two) types:
0
0.5
1
2
3
4
4.5
5
0
0.5
1
2
3
4
4
4
If 𝑉𝑖𝑛 ≤ 𝑉𝐷𝐷 − 𝑉𝑇𝑛
If 𝑉𝑖𝑛 > 𝑉𝐷𝐷 − 𝑉𝑇𝑛
Then 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛
Then 𝑉𝑜𝑢𝑡 = 𝑉𝐷𝐷 − 𝑉𝑇𝑛
Observation #1: Since this logic passes exact 0V for
input 0V but 4V for input 5V, it is said that nMOS
Pass Transistor passes strong LOW but weak HIGH.
Observation #2: To pass Strong HIGH, 𝑉𝐷𝐷 needs to
be higher than 𝑉𝑖𝑛 by 𝑉𝑇𝑛 , meaning 𝑉𝐷𝐷 − 𝑉𝑖𝑛 = 𝑉𝑇𝑛 .
pMOS Pass Transistor:
When pMOS is used as the building block of the Pass
Transistor logic, it is called pMOS Pass Transistor. In
nMOS Pass Transistor, ground (𝑉𝑆𝑆 ) is applied to the gate
( 𝑉𝑆𝑆 = 𝑉𝐺 ). As with nMOS Pass Transistor, the input
voltage is applied to the drain (𝑉𝑖𝑛 = 𝑉𝐷 ), and the output
voltage is taken from the source (𝑉𝑜𝑢𝑡 = 𝑉𝑆 ). The range of
the output voltage can be |𝑉𝑇𝑝 | to 𝑉𝑖𝑛 since 𝑉𝐺𝑆 needs to
be at least −𝑉𝑇𝑝 (generally −1V) to turn ON the nMOS.
1) nMOS Pass Transistor
2) pMOS Pass Transistor
nMOS Pass Transistor:
When nMOS is used as the building block of the Pass
Transistor logic, it is called nMOS Pass Transistor. In
nMOS Pass Transistor, a positive supply voltage (𝑉𝐷𝐷 ) is
applied to the gate (𝑉𝐷𝐷 = 𝑉𝐺 ), the input voltage is applied
to the drain (𝑉𝑖𝑛 = 𝑉𝐷 ), and the output voltage is taken
from the source ( 𝑉𝑜𝑢𝑡 = 𝑉𝑆 ). The range of the output
Fig: pMOS Pass Transistor.
Considering the gate is grounded 𝑉𝑆𝑆 = 0𝑉 and threshold
voltage |𝑉𝑇𝑝 | = 1𝑉 for the pMOS, for different values of
𝑉𝑖𝑛 the values of 𝑉𝑜𝑢𝑡 will be as follows:
Version 9.53 | Page 28 of 36
Imran Chowdhury | Lecture Note | VLSI
𝑽𝒊𝒏 (V)


𝑉𝑆𝑆 = 0𝑉
|𝑉𝑇𝑝 | = 1𝑉
𝑽𝒐𝒖𝒕 (V)
0
0.5
1
1.5
2
3
4
5
1
1
1
1.5
2
3
4
5
If 𝑉𝑖𝑛 ≤ |𝑉𝑇𝑝 |
If 𝑉𝑖𝑛 > |𝑉𝑇𝑝 |
Then 𝑉𝑜𝑢𝑡 = |𝑉𝑇𝑝 |
Then 𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛
Observation #1: Since this logic passes exact 5V for
input 5V but 1V for input 0V, it is said that pMOS
Pass Transistor passes strong HIGH but weak LOW.
Observation #2: To pass Strong LOW, 𝑉𝑆𝑆 needs to
be connected to at least −1V.
Problem 1:
In the following pass transistor logic circuit, if all the
nMOS transistors are identical with a threshold voltage of
1V, what would be the output voltages at P, Q, and R?
Problem 2:
In the following pass transistor logic circuit, if all the
nMOS transistors are identical with a threshold voltage of
1V, what would be the output voltages at P, Q, and R?
Cascading Pass Transistor:
When multiple Pass Transistors are connected such a way
that one Pass Transistor is driving another, it is called
cascading Pass Transistors. Based on the connection
cascading can be be done in 2 (two) ways:
1) Driving next Pass Transistor’s gate (not recommended)
2) Driving next Pass Transistor’s drain (recommended)
The following type of cascading is based on the first
category where one Pass Transistor is driving the gate of
the next one. The problem with this cascading is that, since
the output voltage at drain is dependent on the supply
voltage at gate, at every stage the 𝑉𝑜𝑢𝑡 degrades by 𝑉𝑇𝑛
until it becomes 0. This is why this type of cascading is
not recommended. This type of cascading is not even
possible for pMOS Pass Transistors.
Problem 3:
In the following pass transistor logic circuit, if all the
nMOS transistors are identical with a threshold voltage of
1V, what would be the voltage at each gate?
Problem 4:
In the following pass transistor logic circuit, if all the
nMOS transistors are identical with a threshold voltage of
1V, what would be the voltage at each gate?
Fig: Cascading by driving next pass transistor’s gate.
The following type of cascading is based on the second
category where one Pass Transistor is driving the drain of
the next one. Unlike the first category of cascading, the
output voltage in this cascading does not degrades at every
stage as long as the supply voltage at the gate of every Pass
Transistor is same.
Fig: Cascading by driving next pass transistor’s drain.
Pass Transistor Combinational Logic Design:
A popular and widely-used alternative to complementary
static CMOS is pass-transistor logic, which attempts to
reduce the number of transistors required to implement a
logic circuit by allowing the primary inputs to drive gate
terminals as well as source/drain terminals. This is in
contrast to logic families that we have studied so far,
which only allow primary inputs to drive the gate
terminals of MOSFETS.
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Imran Chowdhury | Lecture Note | VLSI
than that of complementary static CMOS which requires 6
transistors to implement a OR gate.
AND gate using Pass Transistor:
A
Low
Low
High
High




B
Low
High
Low
High
F
Low
Low
Low
High
When input-𝐴 and input-𝐵 both are LOW, gate-𝐵 is
LOW so M1 does not pass input-𝐴. But gate-𝐵̅ is
HIGH so M2 passes input-𝐵 which is LOW.
When input-𝐴 is LOW but input-𝐵 is HIGH, gate-𝐵 is
HIGH so M1 passes input-𝐴 which is LOW. But gate𝐵̅ is LOW so M2 does not pass input-𝐵.
When input-𝐴 is HIGH but input-𝐵 is LOW, gate-𝐵 is
LOW so M1 does not pass input-𝐴. But gate-𝐵̅ is
HIGH so M2 passes input-𝐵 which is LOW.
When input-𝐴 and input-𝐵 both are HIGH, gate-𝐵 is
HIGH so M1 passes input-𝐴 which is HIGH. But gate𝐵̅ is LOW so M2 does not pass input-𝐵.
The number of transistors required to implement an AND
gate using Pass Transistor is 2 + 2 for 𝐵̅ = 4, which is
less than that of complementary static CMOS which
requires 6 transistors to implement an AND gate.
Design Process of AND Gate from the Truth Table:
𝐵 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐵 = 0, 𝐹 = 0
𝑊ℎ𝑒𝑛 𝐵 = 1, 𝐹 = 𝐴




M1 will pass 1 ∙ 𝐵 = 𝐵, and M2 will pass 𝐴 ∙ 𝐵̅
So, output will be 𝐹 = 𝐴 ∙ 𝐵̅ + 𝐵 = 𝐴 + 𝐵
NOT gate using Pass Transistor:
A
Low
High


F
High
Low
When 𝐴 is LOW, gate-𝐴̅ is HIGH so M1 passes input1 which is HIGH. But gate-𝐴 is LOW so M2 does not
pass input-0.
When 𝐴 is HIGH, gate- 𝐴 is HIGH so M2 passes
input-0 which is LOW. But gate-𝐴̅ is LOW so M1
does not pass input-1.
The number of transistors required to implement a NOT
gate using Pass Transistor is 2, which is equal to that of
complementary static CMOS which also requires 2
transistors to implement a NOT gate.
𝐴 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐴 = 0, 𝐹 = 1
𝑊ℎ𝑒𝑛 𝐴 = 1, 𝐹 = 0
OR gate using Pass Transistor:
B
Low
High
Low
High
𝐵 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐵 = 0, 𝐹 = 𝐴
𝑊ℎ𝑒𝑛 𝐵 = 1, 𝐹 = 1
Design Process of NOT Gate from the Truth Table:
M1 will pass 𝐴 ∙ 𝐵, and M2 will pass 0 ∙ 𝐵̅ = 0
So, output will be 𝐹 = 0 + 𝐴 ∙ 𝐵 = 𝐴 ∙ 𝐵
A
Low
Low
High
High
Design Process of OR Gate from the Truth Table:
F
Low
High
High
High
When input-𝐴 and input-𝐵 both are LOW, gate-𝐵̅ is
HIGH so M1 passes input-𝐴 which is LOW. But gate𝐵 is LOW so M2 does not pass input-𝐵.
When input-𝐴 is LOW but input-𝐵 is HIGH, gate-𝐵̅ is
LOW so M1 does not pass input-𝐴. But gate-𝐵 is
HIGH so M2 passes input-𝐵 which is HIGH.
When input-𝐴 is HIGH but input-𝐵 is LOW, gate-𝐵̅ is
HIGH so M1 passes input-𝐴 which is HIGH. But gate𝐵 is LOW so M2 does not pass input-𝐵.
When input-𝐴 and input-𝐵 both are HIGH, gate-𝐵̅ is
LOW so M1 does not pass input-𝐴. But gate-𝐵 is
HIGH so M2 passes input-𝐵 which is HIGH.
The number of transistors required to implement a OR gate
using Pass Transistor is 2 + 2 for 𝐵̅ = 4, which is less
M1 will pass 1 ∙ 𝐴̅ = 𝐴̅, and M2 will pass 0 ∙ 𝐴 = 0
So, output will be 𝐹 = 𝐴̅ + 0 = 𝐴̅
Problem 1:
Implement the Pass Transistor logic circuit for a 2-input
NAND gate, and explain its operation to verify the truth
table.
Problem 2:
Implement the Pass Transistor logic circuit for a 2-input
NOR gate, and explain its operation to verify the truth
table.
Exercise 1:
Implement the Pass Transistor logic circuit for the
Boolean expression 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + (𝐵 ∙ 𝐶).
Solution:
Let’s consider, 𝐹 = ̅̅̅̅̅̅̅̅
𝐴+𝑋
Where, 𝑋 = 𝐵 ∙ 𝐶
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Imran Chowdhury | Lecture Note | VLSI
According to the above breakdown, the 𝑋 (AND gate)
needs to be implemented first to implement 𝐹 (NOR gate).


Implementing the logic circuit for 𝑿:
The transmission gate combines the best of the two
devices by placing an nMOS transistor in parallel with a
pMOS transistor as shown in Figure below. The control
signals to the transmission gate 𝐶 and 𝐶̅ are
complementary to each other. The transmission gate is a
bidirectional switch enabled by the gate signal 'C'.
B
0
0
1
1
C
0
1
0
1
X
0
0
0
1
𝐵 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐵 = 0, 𝑋 = 0
𝑊ℎ𝑒𝑛 𝐵 = 1, 𝑋 = 𝐶
nMOS passes strong LOW (logic 0)
pMOS passes strong HIGH (logic 1)
Fig: Transmission Gate symbols.
According to the transmission gate in the following figure,
M1 will pass 0 ∙ 𝐵̅ = 0, and M2 will pass 𝐵 ∙ 𝐶
So, output will be 𝑋 = 0 + 𝐵 ∙ 𝐶 = 𝐵 ∙ 𝐶


Implementing the logic circuit for 𝑭:
A
0
0
1
1
X
0
1
0
1
F
1
0
0
0
𝐴 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐴 = 0, 𝐹 = 𝑋̅
𝑊ℎ𝑒𝑛 𝐴 = 1, 𝐹 = 0
When C = 1, both MOSFETs are ON and the signal
pass through the gate i.e. A = B if C = 1.
Whereas C = 0 makes the MOSFETs cut off creating
an open circuit between nodes A and B, which
produces a High Impedance (Z) output at B.
C
0
0
1
1
A
0
1
0
1
B
Z
Z
0
1
Fig: Transmission Gate circuit.
Transmission Gate Combinational Logic Design:
M1 will pass 𝑋̅ ∙ 𝐴̅, and M2 will pass 0 ∙ 𝐴 = 0
So, output will be 𝐹 = 𝑋̅ ∙ 𝐴̅ + 0 = 𝐴̅ ∙ 𝑋̅ = ̅̅̅̅̅̅̅̅
𝐴+𝑋
So, the logic circuit for 𝑭 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨 + (𝑩 ∙ 𝑪) will be:
In the previous section, nMOS Pass Transistors were used
to implement logic circuits to reduce the number of
transistors in comparison to CMOS logic circuits. But the
voltage reduction at the output still remains, since nMOS
passes weak HIGH. Transmission Gate logic solves this
issue by connecting a pMOS with the nMOS in parallel,
so that nMOS can be used to pass strong LOW and pMOS
can be used to pass strong HIGH. The fundamental logic
circuit structure of Transmission Gate is same as with the
Pass Transistor logic.
AND gate using Transmission Gate:
Problem 3:
Implement the Pass Transistor logic circuit for the
Boolean expression 𝐹 = 𝐴 + (𝐵 ∙ 𝐶).
Transmission Gate or Pass Gate Logic
A
0
0
1
1
B
0
1
0
1
F
0
0
0
1
The Transmission Gate Logic is developed to solve the
voltage drop problem of the Pass Transistor Logic. This
technique uses the complementary properties of nMOS
and pMOS transistors. i.e.:
Version 9.53 | Page 31 of 36
Imran Chowdhury | Lecture Note | VLSI




When input-𝐴 and input-𝐵 both are ‘0’, TG2 does not
pass anything. But gate-𝐵̅ is HIGH so nMOS of TG1
passes ‘0’, since nMOS is strong to pass ‘0’.
When input-𝐴 is ‘0’ but input-𝐵 is ‘1’, TG1 does not
pass anything. But gate-𝐵 is HIGH so nMOS of TG2
passes 𝐴 or ‘0’.
When input-𝐴 is ‘1’ but input-𝐵 is ‘0’, TG2 does not
pass anything. But gate-𝐵̅ is HIGH so nMOS of TG1
passes ‘0’.
When input-𝐴 and input-𝐵 both are ‘1’, TG1 does not
pass anything. But gate-𝐵̅ is LOW so pMOS of TG2
passes 𝐴 or ‘1’, since pMOS is strong to pass ‘1’.
Design Process of AND Gate from the Truth Table:
𝐵 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐵 = 0, 𝐹 = 0
𝑊ℎ𝑒𝑛 𝐵 = 1, 𝐹 = 𝐴
NOT gate using Transmission Gate:
A
0
1


TG1 will pass 0 ∙ 𝐵̅ = 0, and TG2 will pass 𝐴 ∙ 𝐵
So, output will be 𝐹 = 0 + 𝐴 ∙ 𝐵 = 𝐴 ∙ 𝐵
F
1
0
When 𝐴 is ‘0’, TG2 does not pass anything. But gate𝐴 is LOW so pMOS of TG1 passes ‘1’, since pMOS
is strong to pass ‘1’.
When 𝐴 is ‘1’, TG1 does not pass anything. But gate𝐴 is HIGH so nMOS of TG2 passes ‘0’, since nMOS
is strong to pass ‘0’.
Design Process of NOT Gate from the Truth Table:
OR gate using Transmission Gate:
𝐴 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐴 = 0, 𝐹 = 1
𝑊ℎ𝑒𝑛 𝐴 = 1, 𝐹 = 0
A
0
0
1
1
B
0
1
0
1
F
0
1
1
1
TG1 will pass 1 ∙ 𝐴̅ = 𝐴̅, and TG2 will pass 0 ∙ 𝐴 = 0
So, output will be 𝐹 = 𝐴̅ + 0 = 𝐴̅
Problem 1:
Implement the Transmission Gate logic circuit for a 2input NAND gate, and explain its operation to verify the
truth table.
Problem 2:




When input-𝐴 and input-𝐵 both are ‘0’, TG2 does not
pass anything. But gate-𝐵̅ is HIGH so nMOS of TG1
passes 𝐴 or ‘0’, since nMOS is strong to pass ‘0’.
When input-𝐴 is ‘0’ but input-𝐵 is ‘1’, TG1 does not
pass anything. But gate-𝐵̅ is LOW so pMOS of TG2
passes ‘1’, since pMOS is strong to pass ‘1’.
When input-𝐴 is ‘1’ but input-𝐵 is ‘0’, TG2 does not
pass anything. But gate-𝐵̅ is HIGH so nMOS of TG1
passes 𝐴 or ‘1’.
When input-𝐴 and input-𝐵 both are ‘1’, TG1 does not
pass anything. But gate-𝐵̅ is LOW so pMOS of TG2
passes ‘1’.
Implement the Transmission Gate logic circuit for a 2input NOR gate, and explain its operation to verify the
truth table.
Problem 3:
Name the logic gate that the following circuit operates
like. Explain its operation to verify the truth table.
Design Process of OR Gate from the Truth Table:
𝐵 → 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 𝐼𝑛𝑝𝑢𝑡
𝑊ℎ𝑒𝑛 𝐵 = 0, 𝐹 = 𝐴
𝑊ℎ𝑒𝑛 𝐵 = 1, 𝐹 = 1
TG1 will pass 𝐴 ∙ 𝐵̅, and TG2 will pass 1 ∙ 𝐵 = 𝐵
So, output will be 𝐹 = 𝐴 ∙ 𝐵̅ + 𝐵 = 𝐴 + 𝐵
Version 9.53 | Page 32 of 36
Imran Chowdhury | Lecture Note | VLSI
Problem 4:
Name the logic gate that the following circuit operates
like. Explain its operation to verify the truth table.
silicon wafer is primarily chosen, the fabrication process
can be classified into 3 (three) types:
1) P-well Process
2) N-well Process
3) Dual-well or Twin-tub Process
P-well Process: In this process of CMOS, the substrate or
silicon wafer is chosen to be n-type in which pMOS
devices are formed by suitable masking and diffusion. In
order to accommodate nMOS devices, a deep p-well is
diffused into the n-type substrate.
Problem 5:
Implement the Transmission Gate logic circuit for the
Boolean expression 𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + (𝐵 ∙ 𝐶).
Problem 6:
Implement the Transmission Gate logic circuit for the
Boolean expression 𝐹 = 𝐴 + (𝐵 ∙ 𝐶).
Problem 7:
Write down the truth table of the following logic circuit
where C is the output.
N-well Process: In this process of CMOS, the substrate or
silicon wafer is chosen to be p-type in which nMOS
devices are formed by suitable masking and diffusion. In
order to accommodate pMOS devices, a deep n-well is
diffused into the p-type substrate. N-well CMOS circuits
are superior to p-well because of the lower substrate bias
effect on threshold voltage and inherently lower parasitic
capacitances associated with the source and drain regions.
Twin-tub Process: In this process of CMOS, the substrate
or silicon wafer is chosen to be intrinsic. This allows two
separate tubs to be implanted into the silicon, which in turn
allows the doping profiles in each tub region to be tailored
independently so that neither type of device will suffer
from excessive doping effects. The main advantage of this
process is that the threshold voltage, body effect parameter
and the transconductance can be optimized separately.
For an example, the following CMOS based device is
fabricated based on p-well process.
Fig: Cross-section of a CMOS device based on p-well process.
CMOS Layout Design
After designing the circuit schematic and synthesizing the
operation, the physical circuit/mask layout is designed
which is to be fabricated onto a chip. The layout design
process is done in 2 (two) steps:
CMOS Fabrication Technology
(CMOS Fabrication Process Types)
The CMOS fabrication technology is recognized as the
leader of VLSI systems technology. CMOS provides an
inherently low power static circuit technology that has the
capability of providing lower power-delay product than
bipolar, nMOS, or GaAs technologies. CMOS can be
obtained by integrating both nMOS and pMOS transistors
over the same silicon wafer. Depending on which type of
1) Stick Diagram
2) Mask/Circuit Layout
Stick Diagram
A stick diagram is a kind of diagram which is used to plan
the layout of a transistor cell or a complex circuit. Stick
diagram is a means of capturing topography and layer
information using simple diagrams. It uses "sticks" or lines
to represent the devices and conductors. It acts as an
interface between symbolic circuit and the actual layout.
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Imran Chowdhury | Lecture Note | VLSI
Stick diagram conveys layer information of the CMOS
circuit through:
a) Color codes, or
b) Monochrome encoding
Exercise 1:
Draw the stick diagram of a CMOS inverter.
Solution:
Stick Diagram shows:


Stick Diagram Notations:
all components and vias (interconnections).
relative placement of components.
Stick Diagram does not show:



exact placement of components.
transistor sizes.
wire lengths, wire widths, tub boundaries.
Sick Diagram of a CMOS Inverter:
Some Rules of Sick Diagram:
Rule 1: When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical contact.
Rule 2: When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact (If
electrical contact is needed we have to show the
connection explicitly).
Exercise 2:
Draw the stick diagram of a CMOS 2-input NAND gate.
Solution:
Stick Diagram Notations:
Rule 3: When a poly crosses diffusion it represents a
transistor (if a contact is shown then it is not a transistor).
Sick Diagram of a 2-input NAND gate:
Rule 4: In CMOS, a separation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie on one
side of the line and all nMOS on the other side.
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Imran Chowdhury | Lecture Note | VLSI
Circuit Layout
Hand-drawn Physical Layout of a CMOS Inverter:
VLSI design ultimately aims to translate circuit concepts
onto silicon, which is done by designing circuit layout.
Circuit layout is also called Mask Layout or Physical
Layout. Layout Design is a schematic of the Integrated
Circuits (IC) which describes the exact area and placement
of the components for fabrication. The layout is a physical
representation of circuit design, or the drawing the masks
which will be used in the manufacturing process.
Layout Design shows:
 all components and vias (interconnections).
 exact placement of components.
 transistor sizes.
 wire lengths, wire widths, tub boundaries.
Fig: Physical layout of nMOS (left) and pMOS (right).
Exercise 2:
Draw the physical layout of a CMOS 2-input NAND gate
considering n-well fabrication process.
Solution:
Fig: Layout Design Flow (schematic to physical layout).
Exercise 1:
Draw the physical layout of a CMOS inverter considering
n-well fabrication process.
Solution:
Layout Notations:
Physical Layout of a CMOS Inverter:
Exercise 3:
Draw the physical layout of a CMOS 2-input NOR gate
considering twin-tub fabrication process.
Solution:
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Imran Chowdhury | Lecture Note | VLSI
Exercise 4:
Draw the physical layout of the following CMOS logic
circuit considering twin-tub fabrication process.
𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴 + 𝐵 + 𝐶𝐷
Solution:
Problem 1:
Draw the physical layout of the following CMOS logic
circuit considering twin-tub fabrication process.
𝐹 = ̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴+𝐵+𝐶
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