EE5311- Digital IC Design
Module 3 - The Inverter
Janakiraman V
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai
September 3, 2018
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Learning Objectives
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Explain the functioning of a CMOS inverter
Explain the Voltage Transfer Characteristics of an inverter
Derive an expression for the trip point of an inverter
Derive an expression for the delay of an inverter driving a
load
Derive expressions for Static, Dynamic and Short Circuit
power of an inverter.
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Outline
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Switch Model
Transfer Characteristics
Switching Threshold
Noise Margin
Supply Voltage Scaling
Propagation Delay
Power
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Dynamic
Short circuit
Leakage
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Inverters - Robust Configuration
VDD → 0
VDD → |VT p |
VDD
VDD
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0 → VDD − VT n
0 → VDD
Pull down to GND with NMOS
Pull up to VDD with PMOS
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Load Line
Vin
G
S
D
D
S
Vout
Figure: The CMOS Inverter
IDSp = −IDSn
VGSn = Vin
VGSp = Vin − VDD
VDSn = Vout
VDSp = Vout − VDD
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Load Line
IDn
Vin = 0
Vin = VDD
Vin = 0.7VDD
Vin = 0.4VDD
Vin = 0.5VDD
Vin = 0.7VDD
Vin = 0.4VDD
Vin = 0
Vin = VDD
Vout
Figure: Solid lines- NMOS, Dashed lines - PMOS
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Voltage Transfer Characterisitcs
Vout
Vin
Vout
Vin = VOut = VM
CL
1
2 3 4 5
Vin
Figure: VTC of a CMOS Inverter
Region
1
2
3
4
5
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NMOS
Off
Sat
Sat
Lin
Lin
PMOS
Lin
Lin
Sat
Sat
Off
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Switching Threshold
Vout
Vout
Vin
Vin = VOut =
CL
1
2 3 4 5
Vin
Figure: Switching Threshold
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Both NMOS and PMOS are in saturation
Assume velocity saturation
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Switching Threshold
IDSp = −IDSn
VGSn = Vin
VGSp = Vin − VDD
VDSn = Vout
VDSp = Vout − VDD
Vin = Vout
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Both NMOS and PMOS are in saturation
Assume velocity saturation
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Switching Threshold
Ignoring channel length modulation
Wn
VDSATn
(VM − VTn −
)VDSATn
L
2
Wp
VDSATp
(VM − VDD − VTp −
)VDSATp
= kp′
L
2
V
VTn + VDSATn
+ r (VDD + VTp + DSATp
)
2
2
VM =
1+r
′
kp (Wp /L)VDSATp
Wp vsatp
r= ′
=
kn (Wn /L)VDSATn
Wn vsatn
r
VDD
VM ≈
r +1
IDSn = kn′
IDSp
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Switing Threshold
Vout
Vin = VOut = VM
Increasing r
Vin
Figure: VTC Trip Point
Ratio of
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Wp
Wn
determines VM
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Switing Threshold Without Velocity Saturation
VM =
VTn + r (VDD + VTp )
1+r r
−kp
r=
kn
Left as an exercise
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Noise Margin
Vout
VOH
VOH
NMH
VIH
VOL
VIL VIH
VIL
Vin
NML
VOL
Figure: Noise Margin of a CMOS Inverter
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Logic levels from the driver should be recognized by the
load
Points of slope -1 provide the noise margin levels
NMH = VOH − VIH
NML = VIL − VOL
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Noise Margin Approximation
Vout
VM
VIL
VIH
Vin
Figure: Noise Margin approximation of a CMOS Inverter
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Extend the tangent at VM
Slope is the gain (g ) of the VTC
VM
g
VDD − VM
NML = VIL = VM +
g
NMH = VDD − VIH = VDD − VM +
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Noise Margin Calculations
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Need to consider channel length modulation
out
Slope is the gain (g = dV
) of the VTC
dVin
no−clm
IDSn = IDSn
(1 + λn Vout )
no−clm
IDSp = IDSp (1 + λp (Vout − VDD ))
1 kn VDSATn + kp VDSATp
g =−
ID (VM )
λn − λp
1+r
g≈
(VM − VTn − VDSATn /2)(λn − λp )
kp VDSATp
r=
kn VDSATn
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Pass Transistors
VD
vC (0− ) = 0
VG
VD
vC (0− ) = VDD
VG
vC (t) = min(VG − VTn , VD )
vC (t) = max(VG − VTp , VD )
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Switch Model
Vin = 0
Vin
Vout
Vin = VDD
Rp
Rn
CL
Figure: The CMOS Inverter
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The high and low logic levels are VDD and GND(0)
Logic levels are independent of sizes - Ratioless Logic
Low output impedance (kΩ) - Immune to noise
Large input impedance - Infinite fanout
No conduction path from supply to ground in steady state
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Switch Model Dynamic Behaviour
Vin ↑ VDD
Vin ↓ 0
Rp
Rn
CL
CL
Low → High
High → Low
Figure: Dynamic Behaviour of CMOS Inverter
τrise = Rp CL
τfall = Rn CL
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Delay
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Propagation Delay - 50% input to 50% output
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Rise delay. Output goes from L ↑ H - tpLH
Fall delay . Output goes from H ↓ L - tpHL
t +t
Propagation delay is defined as tp = pHL 2 pLH
Slew
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Rise time - Time taken for output to go from 10% to
90%
Fall time - TIme taken for output to go from 90% to
10%
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Delay
Vin
Vin
Vout
Vout
tpHL
tpLH
CL
t
Figure: Delay
tpHL = Reqn CL
tpLH = Reqp CL
Reqn + Reqp
tp = CL
2
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Transistor Sizing - Symmetric delay
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Rising propagation delay should be identical to falling
propagation delay.
This also ensures a symmeteric VTC
tpHL = tpLH
Reqn = Reqp
CL VDD
CL VDD
=
2IDSATn
2IDSATp
W n µn = W p µp
Wp ≈ 2Wn
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Transistor Sizing - Minimum delay
CL = Cdp1 + Cdn1 + Cgn2 + Cgp2 + Cwire
Reqn + Reqp
2
α
tp = (0.5)[(1 + β)(Cgn2 + Cdn1 ) + Cwire ]Reqn (1 + )
β
Reqp
Wp
α=
@Wp = Wn ; β =
Reqn
Wn
∂tp
=0
∂β
s Cwire
βopt = α 1 +
Cdn1 + Cgn2
tp = CL
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Power Dissipation
Energy lost as heat disspation in the devices
◮ Dynamic - Charge/ Discharging of cpacitance
◮ Short Circuit - Conductive path from VDD → GND
◮ Static - Leakage even when no activity happens
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Dynamic Power
Vin ↑ VDD
Vin ↓ 0
Rp
Rn
CL
CL
Low → High
High → Low
Figure: Capacitor charge and discharge
L↑H
EVDD =
EC =
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Z
∞
iVDD (t)VDD dt
0
Z
∞
iVDD (t)Vout dt
0
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Dynamic Power
L↑H
EVDD =
EVDD =
Z
EVDD =
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Z
∞
0
∞
iVDD (t)VDD dt
CL
0
Z
dvout
VDD dt
dt
VDD
CL VDD dvout
0
2
EVDD = CL VDD
2
CL VDD
EC =
2
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Dynamic Power
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C V2
L ↑ H - Load capacitor charges and disspates L 2DD in
PMOS
C V2
H ↓ L - Load capacitor discharges and disspates L 2DD in
NMOS
Note that the energy dissipated is independent of size
Depends on
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Probability of switching (P0→1 ) - Activity factor
Frequency of operation (f )
2
Pdyn = CL VDD
f0→1
2
Pdyn = CL VDD P0→1 f
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Short Circuit Power
VDD − VT
Vin
Isc
Vout
VT
Ipeak
CL
Figure: Both NMOS and PMOS conduct
IPeak tsc
Ipeak tsc
+ VDD
2
2
Psc = tsc VDD Ipeak f
VDD + VTp − VTn
ts
tsc =
VDD
Esc = VDD
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Static Power
Isubp
0
ON
0
VDD
Isubn
VDD
ON
Figure: NMOS or PMOS leaks current
2
Ptot = (CL VDD
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Pstat = Istat VDD
Ptot = Pdyn + Psc + Pstat
+ VDD Ipeak ts )f0→1 + VDD Ileak
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Stacking Effect
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The intermedaite node : 0 < VX < VDD
Exponentially reduces the leakage of the series stack
(I2 << I1 )
Increase in VTH of the top transistor due to body effect
0
VDD
0
I1
VGS = −VX , VSB = VX
0
0
VDD
VX
0
I2
VGS = 0
IT OP ∝ e(−VX −VT n )/nφt
IBOT ∝ e(−VT n )/nφt
IBOT = IT OP
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Process Variations
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Impossible to manufacture tiny dimensions accurately
Variations are not avoidable
Process Parameters : TOX , NA , Le xj , µn , µp see
variations
Performance Parameters: Currents and Voltages
Process variation information (µ, σ) are provided to
designers
Performance parameter variation in simulation should
match measured variations
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Process Variations
Le
MANUFACTURING
M EAS
ID,1
NA
M EAS
ID,2
M EAS
ID,3
SIMULATION
WAFER : 200mm (8 in) or 300mm (12 in)
SHOULD MATCH
IDSIM
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Global Variations
DIFFERENT
M EAS
ID,1
M EAS
ID,2
CHIP 1
CHIP 2
M EAS
ID,1
M EAS
ID,2
SAME
WAFER : 200mm (8 in) or 300mm (12 in)
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All transistors within a chip affected in the same way
Transistors in different chips across the wafer affected
differently
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M EAS
IDN,1
M EAS
IDP,2
CHIP 2
M EAS
IDN,2
FAST P
CHIP 1
SLOW N
M EAS
IDP,1
SLOW P
FAST N
Global Variations
WAFER : 200mm (8 in) or 300mm (12 in)
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Manufacturing process of (N and P)MOS are different
Transistors end up being Fast (F), Slow (S) or Typical (T)
All N can get biased in one direction
All P can get biased in another
Corner simulation (N,P) : (TT, FS, FF, SF, SS)
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Local Variations
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Transistors sitting right next to each other will be different
Happens mainly due to Random Dopant Fluctuation
Large transistors are affect lesser than small ones
1
(σLocal ∝ √LW
)
Requires large number of statistical simulations to ensure
correct functionality
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Ring Oscillators
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Excellent process monitors
Good representative of all digital circuits
Can be added by the FAB in Kerf regions or by designers
in their chip
Measure the frequency of oscilations to determine the
global process corner
Can be added in multiple corners of a large chip to
measure any across chip variation
2N + 1 Inverters
TP
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Ring Oscillators
2N + 1 Inverters
EN
TP
TP ≈ 2x(2N + 1)τinv
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EN = 0 prevents any oscillations - Saves dynamic power
Usually a couple of 100 INV long
Very high frequency of oscillations
Divided several times before being brought out of the chip
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References
The material presented here is based on the following books/
lecture notes
1. Digital Integrated Circuits Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice
Hall India
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