Problem Sets
&
Lab Examples
Prof. SeongHwan Cho
Dept. of EECS,
KAIST
IDEC 2011
1
Problem #1: Concepts
1. An LC oscillator is a linear time-invariant system if the
input/output signals are in voltage or current domain.
[True False ]
2. A charge-pump PLL is stable if its phase margin in the sdomain is greater than 0o. [True False]
3. Output phase noise a PLL due to the VCO can be
reduced by increasing the loop bandwidth [True False]
4. A PLL will fail to lock if the VCO is not linear.
5. If period jitter is measured for less than 100us, phase
noise below 10kHz offset frequency does not affect the
period jitter.
6. If thermal noise is the only source of noise, phase noise
power of an oscillator is infinity. [True False]
IDEC 2011
2
Problem # 2: Oscillator & Phase Noise
• Suppose an oscillator has phase noise of -100dBc @ 1MHz
offset.
– How much power do you need to increase in order to get 10dB
improvement in phase noise?
– If you put a divide-by-2 after the oscillator, what happens to the
phase noise at the output of the divider?
– Let’s consider the oscillator and divider as a new oscillator. Does
the FOM increase compared to the original oscillator?
/2
IDEC 2011
3
Answer Sheet #2
IDEC 2011
4
Problem #3: Type-I PLL
fref=20MHz, N=50,
Kvco=100MHz/V
ffree= 920MHz
¸N
(a) What is the control voltage when the PLL is in lock?
(b) What is the phase error at the input of the XOR when the
below PLL is in lock?
IDEC 2011
5
Answer Sheet #3
IDEC 2011
6
Lab #1] PLL Design with PLL Design Assistant
• Optimize the loop bandwidth of the below PLL such that its
rms jitter is minimized.
Reference frequency = 10MHz
Output frequency = 1GHz
VCO phase noise: -100dBc @ 1MHz, 1/f corner: 500kHz
Charge-pump noise: -120dBc @ 1MHz , 1/f corner: 100kHz
IDEC 2011
7
Lab #1] PLL Design Assistant
Output frequency: 1.8GHz
Loop bandwidth: 100kHz Loop filter order: 3
Reference frequency: 10MHz
PLL type: 2
Push this button to evaluate
rms jitter
Noise of PFD+CP
Noise of VCO
Order of DSM: 3
Thermal noise level: -100dBc/Hz
Phase noise: -120dBc/Hz @ 1MHz
1/f noise corner frequency: 100kHz
1/f noise corner frequency: 500kHz
IDEC 2011
8
Lab #2] XOR-based PLL using Cadence
• Run a transient simulation of Spectre for the Type-I PLL
in the specified library.
– Does the loop lock? What is the phase difference?
– How can you reduce the ripple on the control voltage?
– What is the settling time?
IDEC 2011
9
Lab #3] PLL Design using Cadence
• Design a Type-II CPPLL that meets the following
specifications.
– Icp=100uA, Kvco=100MHz/V, ffree=50MHz, fref=30MHz,
N=4
– Determine the value of loop filters such that phase
margin = 60, loop bandwidth = 1MHz.
– What is the approximate settling time?
– Zoom into the control voltage. Is it constant? Why or
why not?
IDEC 2011
10
Problem #4: Concepts
1. When designing an integrated LC VCO, it is best to use an
inductor with maximum Q in order to reduce the phase
noise for a given power consumption. [True False]
2. An injection locked frequency divider will oscillate if the input
is absent. [True False]
3. Fractional-N PLL can achieve an arbitrary frequency
resolution, including irrational numbers. [True False]
4. Stability of DSM can be improved by increasing its phase
margin. [True False]
5. Phase noise due to quantization noise can be reduced if
reference frequency is increased. [True False]
6. An all-digital PLL do not need additional low-pass filter
required in analog PLLs to reduce the ripple on the control
voltage . [True False]
IDEC 2011
11
IDEC 2011
12
Problem #5: CP-PLL
VDD
VDD
D
fref
Ip
¸M
vctrl
fout
t
R
VDD
In
D
C
¸N
fref = 40MHz, Ip=110uA, In=100uA, VDD=2V, tau=1ns, M=1, and KVCO=200MHz/V.
• What is the phase error at the input of the
PFD when the PLL is locked?
IDEC 2011
13
Answer Sheet #5
IDEC 2011
14
Problem #6: Fractional-N PLL
D
ref
ctrl
D
vco
div
in
¸ N/N+1
out
N=49, fref = 10MHz
¸2
K
×M
out
SD
Frequency multiplier
1.
2.
Suppose the required output frequency resolution (i.e. step frequency
change) is 10kHz at node out. What should be the minimum input bit
width (K) of the DS modulator?
Suppose the value of frequency multiplier is 4. (i.e. M = 4) What will
happen to the output noise of the DS modulator? (Assume that the DS
is the only source of noise and that the PLL’s loop bandwidth is set so
that the noise of DS modulator is not affected by the PLL in the
frequency of interest.)
IDEC 2011
15
Answer Sheet #6
IDEC 2011
16
Lab #4] Fractional-N PLL using PDA
• Design a PLL that meets the below specification such that
its rms jitter is minimized.
Reference frequency = 10MHz
Output frequency = 1GHz
Frequency resolution = 10kHz
VCO phase noise: -100dBc @ 1MHz, 1/f corner: 500kHz
Charge-pump noise: -120dBc @ 1MHz , 1/f corner: 100kHz
IDEC 2011
17
Lab #5] VCO Design using Spectre
• Design a 2.4GHz VCO.
• Measure its phase noise and determine its FOM.
IDEC 2011
18
Lab #5] PSS Simulation in Spectre
• Beat Frequency:
– Put an approximate oscillating
frequency
• Number of harmonics: 5
• Accuracy: moderate
• Additional Time for
Stabilization: 100n
• Save Initial Transient Results:
yes
• Oscillator: Check!
– Oscillator node: output
– Reference node: gnd
• Options...
– maxtime step: 10ps
IDEC 2011
19
Lab #5] Phase Noise Simulation in Spectre
•
•
•
•
•
•
Sweeptype: Relative
Relative Harmonic: 1
Sweep Range: 10k ~ 10M
Maximum sideband: 5
Output (Choose voltage)
Positive Output Node:
– Frequency output node (+)
• Negative Output Node:
– Frequency output node (-)
• Input Source: none
IDEC 2011
20
Lab #5] Plotting Phase Noise
• Analog Environment 
Results  Direct Plot 
Main Form
• Analysis - pnoise
• Function – Phase Noise
• Plot!
IDEC 2011
21
Lab #6] Fractional-N PLL using Cadence
• Design a Fractional-N Type-II CPPLL that meets
the following specifications.
– Icp=100uA, Kvco=100MHz/V, ffree=50MHz, fref=30MHz,
– fout = 131.2MHz
– Determine the value of loop filters such that phase
margin = 60, loop bandwidth = 1MHz.
– What is the approximate settling time?
– Zoom into the control voltage. Is it constant? Why or
why not?
IDEC 2011
22