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3.
Suppose that the DRAM consists of 32
words, and the cache is direct mapped with
total data capacity of 4 words (i.e. each
block has only one word). The cache was
initially empty, then the following
references (given as word addresses) were
made
1, 17, 24, 6, 0
Which of the above references resulted in
compulsory misses?
a. 1, 17, 24, 6, 0
b. 1, 24, 6
c. 1, 17
d. 1, 0
e. 1
We have a program core consisting of three
conditional branches. The program core will
be executed thousands of times. Below are
the outcomes of each branch for one
execution of the program core (T for taken,
N for not taken)
Branch 1: N, T, T, N
Branch 2: T, N, T
Branch 3: N, T, T, T, T
Assume the behavior of each branch
remains the same for each program core
execution. What is the prediction accuracy
if always not taken branch prediction
scheme was used?
a. 33.3 %
b. 41.7 %
c. 25.0 %
d. 50.0 %
e. 58.3 %
For a computer with a deep pipeline
consisting of 10 pipe stages, what will be
the approximate speedup over a nonpipelined implementation under ideal
conditions and with a large number of
instructions?
a. 5
b. 10
c. 1
d. 20
e. 30
m
a
6.
sa
ee
4.
5.
os
a
2.
Suppose you have a 128 kByte 16 way set
associative cache. Each block in the cache
consists of 32 words. How many blocks in
each way?
a. 64
b. 128
c. 32
d. 16
e. 256
Suppose that the DRAM byte physical
address consists of 32 bits. How many bits
are used for index if we have a direct
mapped cache (size 8kBytes) with 16 word
blocks?
a. 8
b. 7
c. 6
d. 5
e. 4
How many sets does a fully associative
cache has?
a. 1
b. 2
c. 4
d. 8
e. The number of blocks in the cache
Which of the following instructions can
cause a control hazard?
a. lw
b. sw
c. slt
d. beq
e. Any of the above instructions can
cause a control hazard as long as
there is dependency between the
current instruction and subsequent
instructions
d
1.
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7.
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11. What is the total number of bits required to
implement a 32 kByte two way set
associative cache with 2 word blocks, and
each block has 1 valid bit and one dirty bit,
and 15 bits tag?
a. 262144
b. 200704
c. 270336
d. 323584
e. 331776
12. Consider the execution of the following
MIPS instructions on the pipelined CPU
lw $1, 0($2)
add $3, $4, $5
and $6, $7, $8
beq $9, $10, L
or $11, $12, $13
slt $14, $15, $16
How many clock cycles will be needed to
execute the above set of instructions,
assuming that the execution starts with the
lw and ends with the slt instructions
a. 6
b. 7
c. 8
d. 9
e. 10
13. Suppose that the DRAM byte physical
address consists of 32 bits. How many bits
are used for tag if we have a two way set
associative cache (size 2kBytes) with 4 word
blocks?
a. 20
b. 21
c. 22
d. 23
e. 24
m
a
Which of the following data hazards can be
completely solved by forwarding?
a. lw $t5, 24($s2) followed by sub
$t1, $t2, $t5
b. lw $t5, 24($s2) followed by and
$t1, $t5, $t2
c. lw $t5, 24($s2) followed by beq
$t1, $t5, L
d. lw $t5, 24($s2) followed by sw $t5,
0($s3)
e. None of the given choices
9. Suppose that the DRAM consists of 32
words, and the cache is direct mapped with
total data capacity of 4 words (i.e. each
block has only one word). The cache was
initially empty, then the following
references (given as word addresses) were
made
2, 13, 27, 30, 5, 17, 10, 25, 12, 23, 8, 1
What are the final cache contents?
a. 8, 25, 10, 27
b. 12, 17, 30, 23
c. 12, 1, 30, 27
d. 8, 1, 10, 23
e. 12, 23, 8, 1
10. Consider the execution of the following
MIPS instructions on the pipelined CPU
lw $1, 0($2)
add $3, $4, $5
and $6, $7, $8
beq $9, $10, L
or $11, $12, $13
slt $14, $15, $16
Which of the following pairs of instructions
will be accessing the register file at the
same clock cycle?
a. (lw, and), (add, beq), (or, slt)
b. (lw, add), (and, beq), (or, slt)
c. (lw, beq), (add, or), (and, slt)
d. (lw, or), (add, slt)
e. (lw, slt)
sa
ee
d
os
a
8.
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m
a
17. Which of the following methods is used
when there is a cache write miss, where the
word is just written into the cache updating
both the tag and data, no need to check for
cache hit, no need to stall
a. Write-back
b. Write-through
c. Write allocate
d. No-write allocate
e. None of the given choices
18. Suppose that the I-cache miss rate = 1%, the
D-cache miss rate = 2%, the Miss penalty =
100 cycles, the Base CPI (ideal cache) = 1,
Loads & stores are 30% of instructions.
What is the actual CPI?
a. 1.6
b. 2.6
c. 2.0
d. 3.0
e. 4.0
19. Given a CPU base CPI = 1, clock rate = 4GHz,
Miss rate/instruction = 3%, Main memory
access time = 40 ns. What performance
ratio can be achieved of using 2 levels of
caches over using just one level cache if the
access time of the L2 cache = 6 ns and the
global miss rate to main memory = 0.4%?
a. 2.46
b. 2.36
c. 0.38
d. 1.75
e. 0.76
sa
ee
d
os
a
14. What is the purpose of the following set of
conditions
if (ID/EX.MemRead
and ((ID/EX.RegisterRt = IF/ID.RegisterRs)
or (ID/EX.RegisterRt = IF/ID.RegisterRt)))
a. To deal with EX data hazard
b. To deal with MEM data hazard
c. To deal with control hazards
d. To stall the pipeline
e. None of the given choices
15. Suppose you have a 2Gbyte DRAM, what is
the maximum physical word address?
a. 2147483648
b. 2147483647
c. 536870912
d. 536870911
e. 268435455
16. In the pipeline of chapter 4, it was assumed
that the operation times for the major
functional units are 200 ps for memory
access, 200 ps for ALU operation, and 100
ps for register file read or write. Which of
the following statements is correct?
a. The speedup obtained from
pipelining will increase if the time
for an ALU operation can be
shortened by 20%.
b. The speedup obtained from
pipelining will decrease if the time
for an ALU operation takes 20%
more.
c. The speedup obtained from
pipelining will decrease if the time
for an ALU operation can be
shortened by 20%.
d. The speedup obtained from
pipelining will increase if the time
for an ALU operation takes 20%
more.
e. Neither increasing nor decreasing
the ALU operation time would
affect the speedup obtained from
pipelining.
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m
a
23. When is the branch target buffer useful?
a. If hit and instruction is branch
predicted taken
b. If miss and instruction is branch
predicted taken
c. If hit and instruction is branch
predicted not taken
d. If miss and instruction is branch
predicted not taken
e. If hit, no matter whether the
branch is taken or not
24. What are the outputs of the forwarding unit
in the MIPS pipelined CPU?
a. Two control signals to choose the
inputs to the ALU
b. A signal to prevent the PC register
from changing
c. A signal to prevent the IF/ID
register from changing
d. A signal to prevent the ID/EX
register from changing
e. A signal that sets the control bits in
the EX, MEM, and WB control
fields of the ID/EX pipeline register
to 0
25. What is the purpose of the following set of
conditions?
and not (EX/MEM.RegWrite and
(EX/MEM.RegisterRd ≠ 0)
and (EX/MEM.RegisterRd =
ID/EX.RegisterRt))
a. To insert a nop
b. To detect a load-use data hazard
c. To detect a double data hazard
d. To detect a control hazard
e. To detect a data hazard for a
branch
sa
ee
d
os
a
20. Which of the following statements is
correct?
a. The designer of L2 cache should
focus on minimizing hit time
b. The designer of L1 cache should
focus on minimizing miss rate
c. The designer should design L1 and
L2 caches with approximately the
same size as this would probably
achieve the best tradeoff between
performance and complexity
d. Block size for L1 and L2 is of little
importance. So, usually the same
block size is used for both L1 and
L2 caches.
e. Misses depend on memory access
patterns
21. Consider the following MIPS code:
180: sub $10, $4, $8
184: beq $1, $3, 12
188: and $12, $2, $5
192: or $13, $2, $6
196: add $14, $4, $2
200: slt $15, $6, $7
What is the branch target address?
a. 196
b. 200
c. 232
d. 236
e. 784
22. Consider the following MIPS code:
40
sub $11, $2, $4
44
and $12, $2, $5
48
add $1, $2, $1
4C
or $13, $2, $6
50
slt $15, $6, $7
54
lw $16, 50($7)
Suppose that the add instruction above
causes an overflow (which means an
exception), which instructions will be
flushed?
a. add
b. sub, and, add
c. add, or, slt, lw
d. and, add, or, slt, lw
e. sub, and, add, or, slt, lw
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